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simon_tam_gmail
Contributor
Contributor
915 Views
Registered: ‎08-20-2019

VCU TRD PCIe DMA/Bridge blcok

Hi,

   I tried to add PCIe IP in my design based on the VCU TRD PCIe reference in 2019.2. However I noticed some differences in DMA/Bridge subsystem for PCIe IP block between the TRD and what I pulled up from the catalog as shown in the screen captures attached. In the TRD these ports exist: m_axis_cq, m_axis_rc, s_axis_cc, s_axis_rq, pcie4_cfg_control, pcie4_cfg_mesg_rcvd, etc. But these ports don't exist in the same IP block when I get it straight from the Vivado 2019.2 IP catalog. 

   I suspect the DMA/Bridge subsystem for PCIe IP incorporated the PCIe Integrated Block under it and and had done away with these ports in Vivado2019.2. If that is the case I want to make sure this version of DMA/Bridge subsystem for PCIe IP block can still work with the existing PCIe Linux drivers for both the host and device side provided in the VCU TRD 2019.2.

Thanks,

Simon

PCIe_TRD.PNG
Tahiti_PCIe.PNG
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deepeshm
Xilinx Employee
Xilinx Employee
812 Views
Registered: ‎08-06-2008

Hi,

Could you please provide a link on which VCU TRD design you are referring to?

In general, the XDMA IP incorporates both hard block IP and the XDMA bridge wrapper portion. The CQ/CC/RQ interfaces would be inside the IP and wouldn't show up in the XDMA outer interface.

Thanks.

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simon_tam_gmail
Contributor
Contributor
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Registered: ‎08-20-2019

Hi,

   The VCU TRD PCIe reference design I used can be found in the following zip file:

https://www.xilinx.com/member/forms/download/design-license-xef.html?filename=rdf0428-zcu106-vcu-trd-2019-2.zip

   The Wiki page explaining it is below:

https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/176685162/Zynq+UltraScale+MPSoC+VCU+TRD+2019.2+-+PCIe

   I agree all those internal signals such as CQ/CC/RQ should be hidden inside the XDMA IP. The problem is that the XDMA IP only allows one DeviceID. This does not work with the PCIe TRD application/driver. The Wiki page explicitly states that there should be two DeviceIDs (A883 and A884) otherwise the XDMA driver will not work. The TRD PCIe design works because beside exposing internal signals the PCIe Integrated Block allows you to specify multiple DeviceID. 

   So this is where I am stuck on. The TRD obviously works but I can't make my design to match it. Any suggestion is welcome.

Thanks,

Simon

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deepeshm
Xilinx Employee
Xilinx Employee
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Registered: ‎08-06-2008

Thanks for the details. We are looking into it. We will post a reply as soon as we have an update.

Thanks.

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deepeshm
Xilinx Employee
Xilinx Employee
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Registered: ‎08-06-2008

Apologies for the delay on this. I have some more information. The difference in the IP connection that you mentioned is because of a mode that was used in the reference design. This mode allows to use the base IP outside of the XDMA IP. This is just for illustraiton purpose only. The requirement of two Device IDs in the TRD is because the base IP is configured for two physical functions. If you are doing a custom design with XDMA IP, you need not be concerned about needing two Device IDs. The driver that you use for XDMA IP from IP catalog can be downloaded from the link below:

https://github.com/Xilinx/dma_ip_drivers/tree/master/XDMA/linux-kernel

I hope this clarifies. 

Thanks. 

 

 

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simon_tam_gmail
Contributor
Contributor
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Registered: ‎08-20-2019

Hi Deepeshm,

   Thanks for the info. I will let my firmware engineer to know about this. But just in case can you show me how to set this special mode which enables the XDMA IP to come up as base IP so I can connect it just as the TRD?

Thanks,

Simon

 

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