04-11-2012 07:10 AM
I'm simulating my project. I implemented EP. In simple simulation I tried to send from EP to RC TLPs (memory32 writes) with varies length. And I got some confusion, because only from length 2 and above till maxpayload everything ok. TLP with 1DW data payload - transmission halted by Xilinx core.
What is a reason of this problem?
04-17-2012 02:46 PM
How are you checking that the endpoint is stopping the outgoing TLPs with payload of 1DW?
Have you checked cfg_dstatus signals and see if any one of the lower three bits are asserted or not?
Make sure your packets are not malformed for e.g. check length field is set correctly or not. The following AR describes how to do packet PCIe packet analysis: