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Visitor
Visitor
7,162 Views
Registered: ‎04-11-2012

Virtex 5 PCIe minimum payload problem

Hello.

I'm simulating my project. I implemented EP. In simple simulation I tried to send from EP to RC TLPs (memory32 writes) with varies length. And I got some confusion, because only from length 2 and above till maxpayload everything ok. TLP with 1DW data payload - transmission halted by Xilinx core.

What is a reason of this problem?

 

Thanks.

Igor.

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Xilinx Employee
Xilinx Employee
7,134 Views
Registered: ‎08-06-2008

Hi,

 

How are you checking that the endpoint is stopping the outgoing TLPs with payload of 1DW?

Have you checked cfg_dstatus signals and see if any one of the lower three bits are asserted or not?

Make sure your packets are not malformed for e.g. check length field is set correctly or not. The following AR describes how to do packet PCIe packet analysis:

 

http://www.xilinx.com/support/answers/46888.htm

 

Thanks.

DMS

 

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Visitor
Visitor
7,112 Views
Registered: ‎07-07-2009

Check whether your first/last DW enable bits are set correctly. Their format is a little different than for >=2 DW.

 

– Matthias

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Visitor
Visitor
6,953 Views
Registered: ‎08-21-2012

how to simulate the project? can you give me some advice ?

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