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Registered: ‎04-22-2009

Virtex-5 to Virtex-5 PCI Express communication


I am designing a board based on a Virtex-5 FXT and i want to use PCI Express to communicate with external cards. Looking at the architecure of Xilinx evaluation boards, there is a point that i don't understand.


A standrad PCIe system is composed of a Root complex, endpoints, and eventually bridges or switches. The Virtex-5 has only PCIe Endpoint blocks. The AR #31585 confirmed that : "The Xilinx Endpoint Block Plus for PCI Express and Xilinx Endpoint Softcore for PCI Express solutions are Endpoint only solutions and cannot be used in Root Complex, Downstream or Switch configurations".

On the ML555 for instance, no PCI Express reference clock or power supply are generated. The PCIe power supplies and ref. clock come directly from a motherboard (PC for instance) through the PCIe connector of the ML555. In a PCIe system, this card will be used as an endpoint (no rootcomplex, bridges, switches...).


But contrary to the ML555, the ML510 board generates its own ref. clock and power supplies which are distributed to the 2 PCIe slots. So, i suppose that the ML510 can be considered as a motherboard, and that it is possible to plug in it an add-in card which will use the ML510 r ef. clock and power supply (the ML555 board for instance).

But the ML510 is based on a V5, which can not be used in Root complex. Is it possible to create a PCIe communication using only 2 endpoints? For example, is it possible to connect a ML555 board in one of the ML510 PCIe slots and to establish a PCIe communication between the two Virtex-5 ?


If it is not possible, what kind of PCIe add-in card are supported by the ML510 ?


Thank you.

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Xilinx Employee
Xilinx Employee
Registered: ‎08-07-2007

Re: Virtex-5 to Virtex-5 PCI Express communication



If you developed your own PCIe root complex or purchased a root complex core from a 3rd party vendor like NW Logic or PLDA, then you could use that as a root complex on the ML510. The integrated block, itself, on the V5 is an endpoint only configuration.


However, there is also XAPP869 that talks about using two V5s blocks back-to-back in a special configuration, but this is not a true PCIe link. Its a point to point connection using the V5 block and PCIe as a transfer medium, but it should not be considered a root complex type application.