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Visitor
Visitor
514 Views
Registered: ‎11-15-2018

What FPGA is suitable to organize PCI express x1 spec 2.1?

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What FPGA is suitable to organize PCI express x1 spec 2.1?

Maybe also Xilinx has IP blocks ?

I check vivado for Artix and didnt find it

Thinkin tying to realize it on spartan 6 first

But Im not sure on that, can anybody correct me?!

Thanks!

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Moderator
Moderator
399 Views
Registered: ‎06-29-2011

Hi @addi 

I think you are mixing up PCI and PCI Express. Now to clarify the Spartan-6 follows PCIe specification v1.1 and Artix-7 follows PCIe specification v2.1
See the below from the documents of the IPs. I have provided links also.

Spartan-6 UG672 - https://www.xilinx.com/support/documentation/ip_documentation/s6_pcie/v2_4/ug672_S6_IntEndptBlock_PCIe.pdf

garethc_2-1606221913409.png

Artix-7 PG054 - https://www.xilinx.com/support/documentation/ip_documentation/pcie_7x/v3_3/pg054-7series-pcie.pdf

garethc_1-1606221889091.png

 

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Gareth

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Moderator
Moderator
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Registered: ‎06-29-2011

Hi @addi 

Both Artix-7 and Spartan-6 have devices in their respective families that have PCIe blocks that cover this specification. I recommend referring to the data sheets for both the families which will provide more details. I will provide links below.

Spartan-6 Family Overview
https://www.xilinx.com/support/documentation/data_sheets/ds160.pdf

7 Series FPGAs Data Sheet: Overview
https://www.xilinx.com/support/documentation/data_sheets/ds180_7Series_Overview.pdf

Also a very good resource for PCIe questions is the PCIe and CPM Useful Resources sticky post in the forum board. I have also provided a link to this below.

https://forums.xilinx.com/t5/PCIe-and-CPM/PCIE-and-CPM-Useful-Resources/td-p/1079558

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Don’t forget to reply, kudo, and accept as solution.
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Kind regards,
Gareth
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Visitor
Visitor
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Registered: ‎11-15-2018

Thanks a lot! 

Maybe you can also inform about aviability of realization PCI express to Generic local bus on Spartan 6 or Artix7??

Thanks in advance

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Visitor
Visitor
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Registered: ‎11-15-2018

Notices that in Spartan 6 specification approved the following :

PCI (Peripheral Component Interface)
33 MHz and 66 MHz, 3.3V
PCI33_3, PCI66_3 (rising edge) 25 10(2) 0.94 0
PCI33_3, PCI66_3 (falling edge) 25 10(2) 2.03 3.3
HSTL (High-Speed Transceiver

 

Does it means that 250 MB/s cant be realized of PCI express?, according Version 1.x

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Moderator
Moderator
400 Views
Registered: ‎06-29-2011

Hi @addi 

I think you are mixing up PCI and PCI Express. Now to clarify the Spartan-6 follows PCIe specification v1.1 and Artix-7 follows PCIe specification v2.1
See the below from the documents of the IPs. I have provided links also.

Spartan-6 UG672 - https://www.xilinx.com/support/documentation/ip_documentation/s6_pcie/v2_4/ug672_S6_IntEndptBlock_PCIe.pdf

garethc_2-1606221913409.png

Artix-7 PG054 - https://www.xilinx.com/support/documentation/ip_documentation/pcie_7x/v3_3/pg054-7series-pcie.pdf

garethc_1-1606221889091.png

 

-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------

Kind regards,
Gareth

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Visitor
Visitor
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Registered: ‎11-15-2018

Sorry, maybe even on EP4CGX22 its possible to be?

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Scholar
Scholar
353 Views
Registered: ‎08-01-2012

EP4CGX22 is an Altera Device. This is a Xilinx forum. But the EP4CGX22  does have a hard PCIe block.