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buenoshun
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Registered: ‎08-09-2018

What's the difference between TRN and AXI4-Stream interfaces protocols

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What's the difference between TRN and AXI4-Stream interfaces?
I implemented a PCI-express transaction layer logic that worked on the Spartan-6 device, years ago, called pcie_mini or opencores.org. The PCIe endpoint IP had a TRN interface that simply passed the TLP packet to the user logic, my user logic that decoded the TLPs for generating local wishbone bus transactions.
Now I want to make the same thing on Kintex Ultrascale plus device, but its PCIE-EP IP has an AXI4-Streaming interface instead of TRN. It seems a lot more complicated. The specs show that the axi stream has a "descriptor" header with all kinds of data like address and so on. But if a complete TLP is pased to user logic, while the PCIe standard TLP also has most of those fileds.
Question: The Ultrascale-plus PCIe IP Axi bus descriptor is redundant with the TLP header, or the TLP passed to my user logic is incomplete? What should I do with descriptor header, can I just ignore it?
From what I have read, the new core still provides the full TLP, but adds an AXI header to it. The TRN provided only raw data.
When a pcie packet arrives, and I get a TLP on axi, possibly I can reject it. But for read requests, I have to generate a completion packet and assemble an additional AXI header to it, which is a lot of extra work.

 The other thing is if both the TLP header and the axi header contain the same information, then this design from xilinx seems wasteful or redundant. Or if the TLP is truncated and and an AXI header is provided instead of the TLP header, then I need to know about it. Unfortunately I could not find any info about this. The lack of info means the truncation does not happen, or the info is hidden in the documentation?

Is there some reference design with the ultrascaleplus PCIe IP and some memory addressable peripherals? I still want to implement my PCIe to wishbone master logic for low performance peripherals, but for high bandwidth data processing boards the AXI-based bus structure would be used, with some logic decoding the TLPs. Some reference design should have that, lets say with PCIe, DDR and some register file. But I sill need the header decoding info for now.

 

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borisq
Xilinx Employee
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Registered: ‎08-07-2007

hi @buenoshun 

 

Can you answer yes/no to my question: On axi4s pcie EP the full TLP header is still included in the stream in ADDITION to the axi4s (decoded TLP) header? Both, or just one? If both are included, then i can just discard the axi4s header and rely on my existing TLP decoding logic. But if only the new axi4s header is included, then i have to rewrite the whole thing from scratch.

 

- just one. only the AXI4S format is available on Ultrascale/Ultrascale+. 

 

Thanks,

Boris

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borisq
Xilinx Employee
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Registered: ‎08-07-2007

hi @buenoshun 

 

for devices older than spartan-6, we were providing TRN interface.

for devices newer than spartan-6, we provide AXI interface only. so Ultrascale Plus has only AXI interface.

for spartan-6, we provided both TRN and AXI versions PCIe IP.

below is the document for AXI version.

https://www.xilinx.com/support/documentation/ip_documentation/s6_pcie/v2_4/ug672_S6_IntEndptBlock_PCIe.pdf

below is the document for TRN version.

https://www.xilinx.com/support/documentation/user_guides/s6_pcie_ug654.pdf

 

you can find TRN to AXI migration guide in UG672 Appendix J.

 

 

Thanks,

Boris

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buenoshun
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Registered: ‎08-09-2018

Hi, Thanks.

I will study the document chapter J.

Is there an existing wrapper that can be used?

Also, my main issue was about the higher level protocol, not just the bit timing signal. My question was specifically about whether the AXI4S header is redundant with the TLP header, or they are both present in the Ultrascale+ implementation? Is the IP still providing the TLP header after the AXI4S header, or is it removed and decoded into the AXI4S header? And what is the simplest way of creating the completion packet AXI4S header?

regards,

 

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borisq
Xilinx Employee
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Registered: ‎08-07-2007

hi @buenoshun 

 

we provide the example design for you to start.

you can right click on the xci file in Vivado and select Open IP Example Design... then you will see it.

select run simulation you can see the behavior of AXI stream ports.

In the example design, the test bench will write a packet and read it back to verify.

 

below is the answer to your questions.

 

My question was specifically about whether the AXI4S header is redundant with the TLP header, or they are both present in the Ultrascale+ implementation? 

Only AXI4S is available for user logic. i.e., TLP is presented only on the AXI4S interface.

Is the IP still providing the TLP header after the AXI4S header, or is it removed and decoded into the AXI4S header? And what is the simplest way of creating the completion packet AXI4S header?

TLP header is decoded into the AXI4S header. You can reference the example design mentioned above for the cpld generation.

 

Thanks,

Boris

 

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buenoshun
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Registered: ‎08-09-2018

I looked at the example design, but in general Xilinx example designs are quiet confusing, and very different than the simple well structured wishbone systems at Opencores or Altium. My old design decodes the original TLP, I need to know whhether it is still going to receive a full in tact TLP or not.

I dont understand...Can you answer yes/no to my question: On axi4s pcie EP the full TLP header is still included in the stream in ADDITION to the axi4s (decoded TLP) header? Both, or just one? If both are included, then i can just discard the axi4s header and rely on my existing TLP decoding logic. But if only the new axi4s header is included, then i have to rewrite the whole thing from scratch.

 

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borisq
Xilinx Employee
Xilinx Employee
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Registered: ‎08-07-2007

hi @buenoshun 

 

Can you answer yes/no to my question: On axi4s pcie EP the full TLP header is still included in the stream in ADDITION to the axi4s (decoded TLP) header? Both, or just one? If both are included, then i can just discard the axi4s header and rely on my existing TLP decoding logic. But if only the new axi4s header is included, then i have to rewrite the whole thing from scratch.

 

- just one. only the AXI4S format is available on Ultrascale/Ultrascale+. 

 

Thanks,

Boris

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buenoshun
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Thanks.

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