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dhill972
Contributor
Contributor
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Registered: ‎04-02-2013

Why does the PCIe XDMA example design include an unconnected MMCM?

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Can anyone help me understand why there is an unconnected MMCM is in the PCIe XDMA example design?

Is this a bug? 

dhill972_0-1618337506331.jpeg

This is from the 2020.1 XDMA PCIe AXI bridge design example targeting a KCU116. The same MMCM shows up in PCIe DMA mode example design. Unless I missed it this is not documented in  PG197 or PG213.

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deepthi
Xilinx Employee
Xilinx Employee
305 Views
Registered: ‎10-05-2020

Hi @dhill972 ,

PCIe Example design expects a Free-running Clock at the Top level which is required for IBERT/DRP operations.

The top-level file of the generated example design defines the differential input clock.

A clock that is separate from the PCIe reference clock, and not tied to the PCIe reset.

For Further Understanding it, Please go through below link

https://www.xilinx.com/Attachment/Xilinx_Answer_73361_PCIe_Link_Training_Debug_Guide_for_US_and_US_Plus.pdf#page=41

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Don’t forget to reply, kudo, and accept as solution.
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Regards,
Deepthi.

 

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deepthi
Xilinx Employee
Xilinx Employee
306 Views
Registered: ‎10-05-2020

Hi @dhill972 ,

PCIe Example design expects a Free-running Clock at the Top level which is required for IBERT/DRP operations.

The top-level file of the generated example design defines the differential input clock.

A clock that is separate from the PCIe reference clock, and not tied to the PCIe reset.

For Further Understanding it, Please go through below link

https://www.xilinx.com/Attachment/Xilinx_Answer_73361_PCIe_Link_Training_Debug_Guide_for_US_and_US_Plus.pdf#page=41

-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------
Regards,
Deepthi.

 

View solution in original post