cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
ledoute
Visitor
Visitor
3,552 Views
Registered: ‎02-17-2011

XAPP1022 keeps shutting down under Debian Linux

Hello guys,

I'm having a problem with the PCI-E endpoint plus under Linux.

First, I'd like to tell you what I've done already and what I'm trying to do.

 

The used platform is the ML507 Evaluation Board with Virtex-5 FX70.

I have built the PCI-E Endpoint Plus with the supplied example PIO design.

Then I build and inserted the driver from XAPP1022, works fine.

Next I tried the XAPP1022 software example met.cpp which sends random

payload TLP and receives them as well. This works too.

I modified the met.cpp to send defined TLPs instead of randomised ones.

Works fine as well and I also modified the hardware design so I can light

up the leds on the board depending on the payload data.

 

The problem I'm having is that the operating system, Debian Linux, seems

to shut down the driver or something else.

In my opinion it has to do with the PCI-E hotplug support of Linux.

 

So here's what I have to do to get my design to work:

- Start Linux

- Flash the FPGA

- Restart Linux so it detects the PCI-E hardware

- Load the driver and my software

 

and then what happens? If I use the design's reset or wait too long, all

it does is return ffffffff.

As you can see, it's extremely tedious.

 

I don't know if this is due to powersaving in PCI-E or a problem with Linux,

but please, if anyone knows what's causing this or what to try for a solution,

I would be extremely thankful.

 

Best regards

0 Kudos
1 Reply
luisb
Xilinx Employee
Xilinx Employee
3,530 Views
Registered: ‎04-06-2010

The PC enumerates at two different times for PCI Express:

 

1. On a cold boot

2. On a warm boot (restart)

 

If the endpoint is powered and configured by the time the system is up and running, then the PC will not enumerate with the endpoint.  This means that you'll have to wait until a reboot; which is what you're experiencing.

 

If you configure from your PROM, then you won't run into this issue becuase the FPGA will be configured within the 200ms requirement and be able to link train and enumerate.

 

 

0 Kudos