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bolverk
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Registered: ‎09-09-2009

XAPP1052 performance example speed grade question

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Hello,

 

I'm testing my PCIeX8 board that is designed based on XAPP1052.

I built PCIe plus core with 250Mhz user clock option as explained in the XAPP1052 user guide.

After all the process, I could successfully run the performance test application.

 

The question starts here: With user clock option 250Mhz, the example PCIe logic should be

running at 250Mhz, as far as I understand. However, the synthesys report says that the maximum

frequency of the example logic with LX50T-1C is 198.059Mhz as follows; 

 

Timing Summary:
---------------
Speed Grade: -1

   Minimum period: 5.049ns (Maximum Frequency: 198.059MHz)
   Minimum input arrival time before clock: 3.068ns
   Maximum output required time after clock: No path found
   Maximum combinational path delay: 0.000ns

 

Q1) Is it overclocking ?

Q2) Should I user LX50T with higher speed grade ?

         (From my trial, speed grade -3 showed over 260Mhz maximum operation speed)

Q3) If the answer for Q2 is "Yes", ML555 supplied with LX50T-1C is proper for x8 operation ?

 

Any information is appreciated~

Message Edited by bolverk on 09-09-2009 07:24 AM
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perica
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Registered: ‎05-18-2008

Sorry because it is not the exact answer on you question, but I have a question for you.

 

Please can you tell me what version of ISE do you use. I am asking you that because I hadn’t problem with the core when it is generated by some older version of ISE (it works), and when I want to implement PCIe in Virtex5 using ISE 11.2 the design doesn’t work…. I use the same procedure for generating the files.

 

I noticed the same thing as you (timing issue in design) but when you add some extra effort to place and route and maybe preserve hierarchy and without equivalent register removing and register duplication…. Then timing problem disappears.

 

I am not talking that it is good design practice, but…..

 

Thanks,

Petar

Message Edited by perica on 09-26-2009 07:51 AM

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jmonteiro-dme
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Registered: ‎05-15-2009

My shot is that your board oscillator is 200MHz, therefore it can drive the logic at this frequency MAX. However it can take advantage of faster oscillators up tp 250MHz if they are installed (like in user clock slots of the EV boards)

 

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kylocke18
Xilinx Employee
Xilinx Employee
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Registered: ‎08-01-2007

Hello bolverk,

 

The synthesis Timing Summary is basically just an estimate.  At this point in the design, synthesis knows very little about what clock speed the design can actually run at since none of the UCF constraints have been brought into the design flow at this point (UCF is brought in at NGDBuild/Translate).  There are also many things that happen in Map and PAR that affect the "maximum frequency" of the design.

 

I recommend completing the build process at least through PAR and checking the PAR report to see if the design has met timing.  The core is constrained in the UCF to 250 MHz if you generated it that way, so assuming PAR is trying to meet timing on sys_clk period of 4ns, if timing is met the design will work in hardware.

 

-Kyle

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bolverk
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Registered: ‎09-09-2009

 

  Thank you so much Jmonteiro-dme and Kyle.

 

  First, the XAPP1052 logic uses only one external clock - the PCIe system clock which is 100Mhz

  and the internal logic uses derived 250Mhz clock. This internal clock is set in the Logicore block

  creation U/I.

 

  When I did PAR with "Place and Route Mode = Route Only", ISE just went on and the build finished,

  with which I could run the demonstation program. I am not sure the internal operation of the logic

  is normal - one clock could be possibly delayed in some sequential operation.

  However, when I tried PAR with "Place and Route Mode = Multi-Pass Place and Route",

  ISE failed to finish and it showed the errors as in the attached file.

 

  As shown in the UCF file following XAPP1052, this example design uses logic placement to meet 

  timing, but it seems to me that it is not sufficient for x8 lanes' application. Or, I'm doing something

  wrong.

 

  Anybody done XAPP1052 for x8 lanes with LX50T-1C (or ML555) ?

  Any suggestion is appreciated !

ISE10_1-XAPP1052x8-TimingError.JPG
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perica
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Registered: ‎05-18-2008

Sorry because it is not the exact answer on you question, but I have a question for you.

 

Please can you tell me what version of ISE do you use. I am asking you that because I hadn’t problem with the core when it is generated by some older version of ISE (it works), and when I want to implement PCIe in Virtex5 using ISE 11.2 the design doesn’t work…. I use the same procedure for generating the files.

 

I noticed the same thing as you (timing issue in design) but when you add some extra effort to place and route and maybe preserve hierarchy and without equivalent register removing and register duplication…. Then timing problem disappears.

 

I am not talking that it is good design practice, but…..

 

Thanks,

Petar

Message Edited by perica on 09-26-2009 07:51 AM

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bolverk
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Registered: ‎09-09-2009

 

  Thank you perica,

  Your question and recommendation helped me.

 

  I'm using ISE10.1 and I could finally made the example design meet timing with "Place & Route - 5 iterations".

  Also, I heard from my FA that xapp1052 is not so much timing optimized in its original logic design, thus one

  should do some work to meet timing for 8 lane applications.

 

  I hope my experience could be some help for the beginning users of xapp1052.

 

  Have a good day~!

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