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480 Views
Registered: ‎08-10-2018

XC7V2000T 7 Series FPGAs Integrated Block for PCI Express v3.3

I have configured the XC7V2000T in PCIe Endpoint mode.

Is it possible to have a bus master drive a transaction into the PCIE core, go over the link and access data in the PCIE root port (link partner)?

 

Do I simply drive a transaction on the s_axis_tx port for this purpose?

I assume then the read data will return on the m_axis_rx port.

 

Can you please confirm this?

 

thanks!

Abhishek

 

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Xilinx Employee
Xilinx Employee
395 Views
Registered: ‎08-06-2008

Re: XC7V2000T 7 Series FPGAs Integrated Block for PCI Express v3.3

Yes that is correct. You would need information of the address you will be reading from the host.

Thanks.