I'm trying to understand XDMA IP via example design, however I have a hard time for it.
I'm using AXI4 Memory Mapped Example like below picture.
When I run simulation of example design,
first card's input port(rp_pci_exp_txp) value comes with values (0000, ffff),
after long time card's output port(ep_pci_exp_txp) have values (Z -> ffff).
But there is no signal changed even AXI signals!
How does DMA module know when to send data?
Also what the initial? values 0000, ffff means?
And after very long long time, xdma's m_axi_awvalid turn into value 1 and after that other axi_write signal also operate.
How does DMA module know when to operate AXI?
And I'm trying to access BRAM with my logic.
Is it okay share xdma_app's slave signal??