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candycrush
Contributor
Contributor
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Registered: ‎11-28-2018

XDMA example design

Hi,

I'm trying to understand XDMA IP via example design, however I have a hard time for it.

I'm using AXI4 Memory Mapped Example like below picture.

When I run simulation of example design,

first card's input port(rp_pci_exp_txp) value comes with values (0000, ffff),

after long time card's output port(ep_pci_exp_txp) have values (Z -> ffff).

But there is no signal changed even AXI signals!

How does DMA module know when to send data?

Also what the initial? values 0000, ffff means?

candycrush_1-1617179506579.png

 

And after very long long time, xdma's m_axi_awvalid turn into value 1 and after that other axi_write signal also operate.

How does DMA module know when to operate AXI?

 

And I'm trying to access BRAM with my logic.

Is it okay share xdma_app's slave signal??

 

Thank you!!

 

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