02-03-2021 03:05 AM
I am using xdma ip for pcie with vu7p.
After programming bitstream file into fpga, the areset_n signal(output of ip) of xdma ip is held as low. It does not come back to high. Axi_aclk's status is normal.
But abnormally, areset_n is held as low. So the modules which is connected with areset_n of xdma ip is on reset.
Now, since fpga is not connected with pcie host, the pcie link-up is low. I think it does not care between link-up and areset_n.
How can i solve this problem? What is involved in Areset_n of xdma
02-04-2021 12:02 AM
the user logic connected to PCIe should keep reset if PCIe does not work , this is expected
However if you expect the user logic to work, regardless of the status of the link up signals, you will need to add extra logic to MUX the reset logic
02-25-2021 06:34 AM - edited 02-25-2021 06:41 AM
I have the same problem. I use XDMA IP core on xcku5p-ffvb676,VIVADO is 2019.2
First I use the UltraScale+ PCI Express Integrated Block IP v1.3 to test the hardware,the host PC can recognize the PCIE device as a PCI Memory Controller device.
Then I use XDMA IP and generated an example design.
I download the example design's bit and reboot the host PC,but the PC can't recognize the PCIE device.
I added the ila in the example design and saw the xdma's output axi_aclk user_clk is right but the signals user_resetn and user_lnk_up held low.
I think the xdma IP is not worked.But it's only an example design, I just added the PIN numbers and IO standard. I do not know where is the problem.
02-26-2021 02:55 AM
Today I use other PCIE card with xc7k325tffg900,do the same work as xcku5p-ffvb676.
The XDMA example design bit download to the K7 card. The host PC can recognize the K7 card.
03-02-2021 12:31 AM
The problem is solved.
Maybe the problem is a bug of vivado 2019.2.
Create a new project, project device must set to kcu116 and generate the XDMA IP then copy the new IP to the original project.