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younggeun
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Registered: ‎12-21-2020

Xdma axi_aclk question

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I am using xdma ip as pcie 2.0 with virtex ultrascale+.

Xdma ip has axi_aclk. And in the datasheet of datasheet. It describes axi_aclk is not a freerun clock.

If it is not freerun clock, what case will be problem? The clock will be deasserted in what case??

Thanks

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kurihara
Xilinx Employee
Xilinx Employee
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Registered: ‎07-26-2012

Yes. axi_aresetn is deasserted just before user_lnk_up. You can safely use this clock with a link-up and the reset released.

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kurihara
Xilinx Employee
Xilinx Employee
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Registered: ‎07-26-2012

axi_aclk is made from txoutclk of gt. Therefore, the clock is not output at startup or reset. For this reason, do not design to expect axi to work when PCIe starts up or resets.

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younggeun
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Registered: ‎12-21-2020

Then, do you mean this clock is safe when the status of pcie link-up is safe? and this clock is fully dependent of pcie link up status?  is it right?

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kurihara
Xilinx Employee
Xilinx Employee
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Registered: ‎07-26-2012

Yes. axi_aresetn is deasserted just before user_lnk_up. You can safely use this clock with a link-up and the reset released.

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