09-06-2019 12:21 PM
Hello, I have an Alveo U250 Data Center card plugged into my motherboard and have uploaded the Xilinx Virtual Cable example design explained in Using the PCIe-XVC-VSEC Example Design subsection of PG213 (v1.3) UltraScale+ Devices Block for PCIe v1.3. The PCIe endpoint enumerates with the OS on the host machine. I have changed identifications on the PCIe IP as shown.
The host is a 64-bit system running CentOS 7.
# lscpu Architecture: x86_64 CPU op-mode(s): 32-bit, 64-bit Byte Order: Little Endian CPU(s): 4 On-line CPU(s) list: 0-3 Thread(s) per core: 1 Core(s) per socket: 4 Socket(s): 1 NUMA node(s): 1 Vendor ID: GenuineIntel CPU family: 6 Model: 45 Model name: Intel(R) Xeon(R) CPU E5-1607 0 @ 3.00GHz Stepping: 7 CPU MHz: 1246.215 CPU max MHz: 3000.0000 CPU min MHz: 1200.0000 BogoMIPS: 5985.74 Virtualization: VT-x L1d cache: 32K L1i cache: 32K L2 cache: 256K L3 cache: 10240K NUMA node0 CPU(s): 0-3 Flags: fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe syscall nx pdpe1gb rdtscp lm constant_tsc arch_perfmon pebs bts rep_good nopl xtopology nonstop_tsc aperfmperf eagerfpu pni pclmulqdq dtes64 monitor ds_cpl vmx smx est tm2 ssse3 cx16 xtpr pdcm pcid dca sse4_1 sse4_2 x2apic popcnt tsc_deadline_timer aes xsave avx lahf_lm epb ssbd ibrs ibpb stibp tpr_shadow vnmi flexpriority ept vpid xsaveopt dtherm arat pln pts md_clear spec_ctrl intel_stibp flush_l1d
# uname -a Linux 3.10.0-957.27.2.el7.x86_64 #1 SMP Mon Jul 29 17:46:05 UTC 2019 x86_64 x86_64 x86_64 GNU/Linux
My assumption at this point is that the hardware was built correctly because when I lspci I do see the endpoint as mentioned above
# lspci | grep Xil 04:00.0 Memory controller: Xilinx Corporation Device beaf
I am now trying to get the driver verified before I begin using the server application. I seem to be able to install the driver and load it into the kernel as documented in the guide. However when I try to compile and run the test application, I get the following error.
# ./driver_test/verify_xil_xvc_driver Test Length: 32, pattern abcdefgHIJKLMOP FAILURE Byte 0 did not match (0x61 != 0x41 mask 0xFF), pattern abcdefgHIJKLMOP
Since everything else appears to be working (character device creations, driver registrations, non-error return codes from ioctl), I am really not sure where to start debugging from. I was wondering if anyone has experience with this example design and could give me some guidance.
09-09-2019 06:38 AM
So I am looking through the RTL and it looks like the vsec is instantiated like this.
vsec_null #( .EXT_CONFIG_BASE_ADDRESS(12'h480), .EXT_CONFIG_CAP_LENGTH(12'h010), .EXT_CONFIG_NEXT_CAP(12'h000), .PCIE_VSEC_ID(16'h0000), .PCIE_VSEC_REV(4'h0) ) vsec_null_i ( // Control signals .clk(user_clk), // PCIe Extended Capability Interface signals .read_received(cfg_ext_read_received), .write_received(cfg_ext_write_received), .register_number(cfg_ext_register_number), .function_number(cfg_ext_function_number), .write_data(cfg_ext_write_data), .write_byte_enable(cfg_ext_write_byte_enable), .read_data(null_vsec_read_data), .read_data_valid(null_vsec_read_data_valid), // IO to and from the user design. .status_reg_in(pcie_vsec_loopback), .control_reg_out(pcie_vsec_loopback) );
When the driver registers, it finds the base address offset at 0x100 rather than 0x480.
[ 238.198966] xilinx_xvc_pci_driver: Starting... [ 836.558623] xilinx_xvc_pci_driver: Cleaning up resources... [ 859.006091] xilinx_xvc_pci_driver: Starting... [ 859.007131] xilinx_xvc_pci_driver: Created device 0 xil_xvc/cfg_ioc0, reg offset (0x100)
Not sure why the software is finding 0x100 rather than 0x480 or which address should be the real offset.
09-10-2019 03:57 AM
Can you clarify what driver this is that you are using and where you got this from?
09-10-2019 04:26 AM
Linux Driver for Xilinx XVC Over PCIe
Per PG213 (v1.3) June 24, 2019 UltraScale+ Devices Block for PCIe v1.3
1. Copy the ZIP file from the Vivado install directory to the FPGA connected Host PC and extract (unzip) its contents.
This file is located at the following path within the Vivado installation directory. XVC Driver and SW Path: …/data/xicom/driver/pcie/xvc_pcie.zip
The README.txt files within the driver_* and xvcserver directories identify how to compile, install, and run the XVC drivers and software, and are summarized in the following steps. Follow the following steps after the driver and software files have been copied to the Host PC and you are logged in as a user with root permissions.