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Observer chintan_tag
Observer
356 Views
Registered: ‎12-03-2018

ZC706 PCIe TRD Question

Hello,

I am new to the Zynq7000 series as well as PCIe . I have a ZC706 eval card and I am trying to implement a subset of the functionality implemented in the PCIe TRD. Specifically, my application only needs to send streaming data to the host over PCIe (one direction only). Clearly I can remove the Video processing elements of the TRD, but for the PCIe block will I still need the NWL AXI DMA? My use case is very narrow and well-defined - need to convert AXI-streaming to fixed size data packets to be sent over the PCIe, so wondering if I can get away with simpler "from-scratch" logic to interface with the PCIe block directly without the NWL module.

A different PCIe related question. In PCIe, can the peripheral/endpoint request to send data to the host, or does the host need to send a read request first to initiate the data transfer. I think setting the peripheral in "bus master" mode would allow peripheral to send data to host (via DMA), but any experts who can shed more light on this, would be much appreciated.

 

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2 Replies
Moderator
Moderator
311 Views
Registered: ‎02-16-2010

Re: ZC706 PCIe TRD Question

@chintan_tag

Can you check "axi memory mapped to PCIe" IP? With this IP, you can initiate a memory write to host similar to a write transaction initiated on AXI4 bus.

You will need to set the AXI BAR to PCIe BAR translation address so that the AXI transaction is translated as a memory write TLP by the IP.

Please check PG055 for more details about the IP.

For data transfer from EP to RP, you can set "Bus master" bit in the configuration space of EP and initiate the transfer.

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Observer chintan_asi
Observer
281 Views
Registered: ‎11-05-2018

Re: ZC706 PCIe TRD Question

Venkata,

Thanks for the response. If one to compare the PG55(axi memory mapped to PCIe) vs PG195 ( Xilinx® AXI Bridge for PCI Express® Gen3 Subsystem), I understand the Gen 3 PCIe will be faster because it supports 8GT vs Gen 2 (5GT), and that the PG 195 supports a larger max payload size (256 vs 512/1024). Other than those two, is there any architectural (or other) difference that makes the PG55 slower in sending high-speed data from PCIe endpoint to host. I am trying to ascertain if we should move to a Ultrascale+ part to accomodate the Gen3 PCIe core (and newer AXI-PCI bridge) or if the Zynq 7000+ part (with PCI Gen 2) will suffice.

I guess put simply, what are benchmark throughput numbers for PCIe endpoint-to-host data transfer using PG 55, if they are available?

Thanks
Chintan

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