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Observer bchetwynd
Registered: ‎05-07-2015

ZC706 - PCIe XDMA Core and Clock Constraints

Hello.  There seems to be similar posts, but none seem to get to the crux of my issue.  For reference, I am using Vivado 2018.2 and the ZC706.  I started with the reference Zynq design and added a XDMA Core.  Here is my block diagram:


My current XDC file is:

# PCIe Reset
set_property IOSTANDARD LVCMOS15 [get_ports pcie_rst_n]
set_property PULLUP true [get_ports pcie_rst_n]
set_property PACKAGE_PIN AK23 [get_ports pcie_rst_n]

# PCIe Clock
set_property LOC IBUFDS_GTE2_X0Y7 [get_cells -match_style ucf */pcie_clk_buf]
set_property PACKAGE_PIN N8 [get_ports pcie_clk_p]
set_property PACKAGE_PIN N7 [get_ports pcie_clk_n]

# Clock Constraints
create_clock -period 10.000 -name pcie_clk_p -waveform {0.000 5.000} [get_ports pcie_clk_p]


I have tried many different permutations of constraints to get the design to build.  Here is my current messages:


Even if I take out the PACKAGE_PIN constraints and the LOC constraints, it complains about the I/O Standard being DEFAULT.  If I try to address that, it also complains.

In summary, I am just looking for the couple of XDC lines that will allow me to properly use the 100MHz PCIe clock in my design.

Thank you,


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1 Reply
Registered: ‎02-16-2010

Re: ZC706 - PCIe XDMA Core and Clock Constraints


Try by removing the constraint below.

set_property LOC IBUFDS_GTE2_X0Y7 [get_cells -match_style ucf */pcie_clk_buf]

Since you have the LOC constraint on pcie_clk_p/n, Vivado will automatically choose the correct location for pcie_clk_buf primitive in your design.

Don't forget to reply, give kudo and accept as solution
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