12-08-2013 09:37 PM
I got some questions about PCIe TLP on 32-bit and 64-bit system:
1. On a 32-bit system, if a PCIe device send a memory write TLP with 64-bit address ( 4 DW header ), and the up 32-bit of the address is not 0, what will happen?
2. On a 64-bit system, a TLP with 32-bit address data write, what is the result?
12-10-2013 10:55 AM
To start off, the PCI Express specification REQUIRES that the upper 32-bit address of a 4DW TLP not be zero! If it is, the vast majority of chipsets that strictly follow the PCIe spec will drop the packet as malformed.
The answer to #2 is pretty straight forward. The data of a 3DW TLP will be written somewhere in the lower 4GB of memory space, as that's all that it can address.
As for answer #1, i am not 100% certain, but i believe that it will simpy ignore the upper 32-bits and write to the lower only.
04-03-2014 09:01 AM
I have once used v6 core 1.3 + xapp1052 core in my device. But I found when the device sent read TLP or write TLP to host with 64 bit address(Upper 32 is all 0) to the host (32 CentOS with PAE),the host OS just hang on.I think the V6 core would drop the packet as malformed.I will try it.
04-05-2014 07:56 AM