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Contributor
Contributor
11,605 Views
Registered: ‎01-07-2014

axi pcie memory mapped: v2.5, speed question

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Hello,

 

 I've just switched to Vivado 2014.4. In this version,the AXI MM PCIe IP (axi_pcie) is upgraded to v2.5.

 

In my design, I use the 5GT/s x8 configuration. This configuration cannot be selected in the GUI IP customization

tool. I should note it worked fine in Vivado 2014.2.

 

The change log lists only minor changes.

 

My questions are:

 

- Should 5GT/s x8 configuration work with axi_pcie v2.5 ?

 

- Is it just a GUI tool bug? Should I be able to get the design work in my config. by forcing 5GT parameter

directly in RTL?

 

Thank you,

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Scholar
Scholar
19,608 Views
Registered: ‎02-03-2010

Hi

 

The core is supposed to support only x4gen2 or x8 gen1. not gen2 x8.

http://www.xilinx.com/support/answers/61248.html

 

I think it got corrected in latest release.

 

Regards,

KR

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Scholar
Scholar
11,572 Views
Registered: ‎02-03-2010

Hi,

 

What is the device you are tagetting includint he speed grade.

 

Regards,

KR

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Contributor
Contributor
11,555 Views
Registered: ‎01-07-2014

My target is: XC7Z045 FFG900, grade -2

 

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Scholar
Scholar
19,609 Views
Registered: ‎02-03-2010

Hi

 

The core is supposed to support only x4gen2 or x8 gen1. not gen2 x8.

http://www.xilinx.com/support/answers/61248.html

 

I think it got corrected in latest release.

 

Regards,

KR

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Contributor
Contributor
11,430 Views
Registered: ‎01-07-2014

Thanks for confirming.

 

Are there plans to make Gen2 x8 mode available in future releases of axi pcie?

 

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Scholar
Scholar
11,331 Views
Registered: ‎02-03-2010

Hi ,

 

I think there is restriction of Bridge logic to work with 256 bit interface at 250MHz  which is essential to manage x8 gen2 (40G data rate at line side).

 

Regards,

KR

 

 

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Explorer
Explorer
10,182 Views
Registered: ‎09-19-2010

Hi, 

 

Just a simple math says me 128 bits * 250 MHz = 32 Gbits/s which is the actual (data) rate of pcie gen2 x8. (4 gbits/s each line and 8 lines) 

 

what is the need for a 256 bits width interface? 

 

furthermore, the 7 series integrated block for pci express (v3.0) also uses a 128 bits width link in gen2 x8 mode. 

 

so i don't get it why the bridge core does not support gen2 x8?

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