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xiaohu125
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Registered: ‎06-13-2014

confusion about xdma pg195

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Hi, all

I am using xilinx xdma ip(pg195-pcie-dma.pdf), vivado 2017.4, a custom board with pcie pin and ddr3.

I have a confusion on figure 2-6 (DMA/Bridge C2H Transfer Summery) when reading through pg195 document. On the top of the figure, it says "Application program initiates C2H Tranfer, with transfer length, receive buffer location".So I think that , suppose now I want transfer the ethernet data received from RJ45 of my board, to pc host memory(data path is RJ45 -> DDR3 on board -> host memory), So:

1.  How does the pc application program get to know when to initiates C2H transfer ? If the application program initiates too early, maybe there is no data in board ddr3, therefore host will get nothing.

 

 

 

 

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peimann
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Registered: ‎10-03-2018

Good morning @xiaohu125 

Yes, to initiate DMA transfer from the FPGA, you will have to build the descriptors and initiate the DMA transfer.  It will then behave just as if the host system had initiated the transfer. 

There are several threads in the Xilinx Forum which discuss how this is approached.  Although they are mostly questions, rather than tutorials.  Assuming that your host system is Linux or Windows, be sure that you have all of the target memory locked down, so that it is consistently accessible from the FPGA.  This is one of the most difficult parts of the process. 

Note that the system page tables may be involved in DMA transfer.  I haven't had any difficulty on this subject, however I have been pushing and pulling from the card, not using card initiated transfer.  One of the PCI engineers at Xilinx should be able to help you, if you file a help request.  These people are very knowledgable, and have saved my FPGA designers a great deal of effort and experimentation. 

That said, my application is currently using a relatively slow polling loop to transfer roughly 1.8 GiByte/second to the FPGA.  Using 32 MiByte transfers, with tripple buffering on each side, I can poll as slowly as once every ten milliseconds (100 Hz) without transfer failure. 

Interrupts are initiated by the FPGA.  There are three sorts, although I expect that you will end up using MSI-x. 

Here is a short description: https://electronics.stackexchange.com/questions/76867/what-do-the-different-interrupts-in-pcie-do-i-referring-to-msi-msi-x-and-intx

For a complete discussion of how interrupts are serviced, take a look at the Linux Kernel documents on PCI.  They are really quite complete.  If you are dealing with Windoze, you have my sympathy. 

Luck!

Kind Regards,
Peimann, S. M.
----
Toddlers are the Storm-Troopers of the Great God Entropy.
Physics: Not Just a Good Idea, It's THE LAW.

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peimann
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Registered: ‎10-03-2018

Good morning @xiaohu125,

If your FPGA has memory available, it can be read, although there may be no useful information at the read location.  It will simply be in its initial boot state, if naught else. 

When to initiate transfer can be done by exposing a register and polling it. 

A more sophisticated approach would be to use a PCIe interrupt to the CPU.  This might require that you do some custom device driver development, however.  I'm not certain if I can simply use the ::select function to wait for one in an application. 

Finally, you can allocate and lock a memory buffer, and simply initiate DMA transfer from the FPGA.  This will require that you configure addresses across the PCIe bus, and then the FPGA can do its part. 

I'm not an expert.  I'm using the example from the Xilinx Answer Record 65444, and building atop that.  I'm not going to change the drivers until I have to. 

Luck!

Kind Regards,
Peimann, S. M.
----
Toddlers are the Storm-Troopers of the Great God Entropy.
Physics: Not Just a Good Idea, It's THE LAW.
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andrewlan
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Registered: ‎06-25-2014

I suppose the wording "Initiates transfer" could be a bit confusing. What is going on, is the application is setting up the transfer with respect to size and location and passes this information to the DMA SW driver which in turn breaks this up into buffer descriptors. These descriptors are then made available to the HW DMA controller which under the flow control of the master (i.e. In your example ethernet) will move data. If the master is throttled (i.e. there are no buffer descriptors available) then data will not be moved, so the game in a real time application (e.g. Master data from an ADC) is always keeping the buffer descriptors topped up by monitoring the DMA status and initiating further transfers.

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xiaohu125
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Registered: ‎06-13-2014
hi, Peimann

Your first method is easy to understand, maybe I will implement it. The second method, that is using interrupt, is difficult for me, since I am not familiar interrupt, and do not know how to send a specified interrupt to cpu as there are too many interrupt vectors to choose. I am interesting in the last method, but I do not understand how to initiate dma from FPGA that is which work should FPGA do to act as a master, i.e. Does FPGA need generate description list in bram?

Thank you , Have a nice day !
xiaohu125
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peimann
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Registered: ‎10-03-2018

Good morning @xiaohu125 

Yes, to initiate DMA transfer from the FPGA, you will have to build the descriptors and initiate the DMA transfer.  It will then behave just as if the host system had initiated the transfer. 

There are several threads in the Xilinx Forum which discuss how this is approached.  Although they are mostly questions, rather than tutorials.  Assuming that your host system is Linux or Windows, be sure that you have all of the target memory locked down, so that it is consistently accessible from the FPGA.  This is one of the most difficult parts of the process. 

Note that the system page tables may be involved in DMA transfer.  I haven't had any difficulty on this subject, however I have been pushing and pulling from the card, not using card initiated transfer.  One of the PCI engineers at Xilinx should be able to help you, if you file a help request.  These people are very knowledgable, and have saved my FPGA designers a great deal of effort and experimentation. 

That said, my application is currently using a relatively slow polling loop to transfer roughly 1.8 GiByte/second to the FPGA.  Using 32 MiByte transfers, with tripple buffering on each side, I can poll as slowly as once every ten milliseconds (100 Hz) without transfer failure. 

Interrupts are initiated by the FPGA.  There are three sorts, although I expect that you will end up using MSI-x. 

Here is a short description: https://electronics.stackexchange.com/questions/76867/what-do-the-different-interrupts-in-pcie-do-i-referring-to-msi-msi-x-and-intx

For a complete discussion of how interrupts are serviced, take a look at the Linux Kernel documents on PCI.  They are really quite complete.  If you are dealing with Windoze, you have my sympathy. 

Luck!

Kind Regards,
Peimann, S. M.
----
Toddlers are the Storm-Troopers of the Great God Entropy.
Physics: Not Just a Good Idea, It's THE LAW.

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xiaohu125
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Registered: ‎06-13-2014
Hi, Peimann :

I am really thankful to you for responding to my query and your advice was really helpful and wonderful.

Best Regards,
xiaohu125
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peimann
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Registered: ‎10-03-2018

Good Afternoon @xiaohu125 ,

Glad that I could be of help.

Good luck!

Kind Regards,
Peimann, S. M.
----
Toddlers are the Storm-Troopers of the Great God Entropy.
Physics: Not Just a Good Idea, It's THE LAW.
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