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Visitor
Visitor
3,558 Views
Registered: ‎05-18-2010

downsport can't receive memory write request

Hi,

   I am simulating PCIE on modelsim SE6.5.  I connect my own PCIE (X8) DMA design to downsport (provided by IP core).

   When I transmit Memory write, CPLD,memory read from downsport to my design, and transmit CPLD or Memory read from my design to downsport, everything works correctly.

 

  However,when transmit Memory read with data from my own design to downsport, strange things happens. The data transmitted on the PCIE's locallink interface of my design  is correct,but downsport never receive anything. (I connect txp,txn ,rxp,rxn of my deign to rxp,rxn,txp,txn of downsport).  Of course,when I use TSK_EXPECT_MEMWR,it returns nothing.In the error.dat file,no error is recorded.

 

   In the configuration space ,I set Base Address register,command register and device control register.

TSK_TX_TYPE0_CONFIGURATION_WRITE(DEFAULT_TAG,12'04,32'h00000007,4'h1);

TSK_TX_TYPE0_CONFIGURATION_WRITE(DEFAULT_TAG,12'68,32'h00002850,4'h3);

I don't know why,why the downsport can't receive DMA's memory write request. Please help.

 

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2 Replies
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Explorer
Explorer
3,554 Views
Registered: ‎10-01-2008

Hi,

 

I am guessing you are running into this issue. Hope this AR will fix your problem.

 

http://www.xilinx.com/support/answers/33918.htm

 

BR,

Yan Shun Li

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Visitor
Visitor
3,528 Views
Registered: ‎05-18-2010

Hi,

  Thank you very much for your quick reply. It is quite helpful to me .

  I have found where my problem comes from. In my PCIe DMA project, I send memory write TLP with 128DW data. However,the max payload in device control register of downsport is "000",which represent that the max payload is 32DW.

 

   I tried your suggestion,but I still can not change the device control register of downsport to 'h285f.  When implement TSK_READ_CFG_DW, it work correctly,and cfg_rd_wr_done_n of downsport will set 0. But when implement TSK_WRITE_CFG_DW, nothing changed in downsport's configuration space,and cfg_rd_wr_done_n never goes 0.

It seems the downsport doesn't support configuration write.

 

   Additional,in AR#33918,the first step is to change file pcie_2_0_rport_v6.v, but the IP core "Endpoint block plus for PCI Express" doesn't generate this file.

  What should I do ,Please help.

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