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Observer
Observer
8,710 Views
Registered: ‎05-28-2011

in simulation BMD Not read request and completions

Hi all,

I want to simulate BMD by modelsim se 6.5.

I have a htg v5 fx100t board , and now i am trying to understand how BMD (xapp1052) works  .  i did it step by step like this

 

1. I generated the  integrated block for pci express v1.15 (verilog)

2. after that i put folder from  xapp1052.zip in my PCIe folder

3. for Simulation i used all source files in folder dsport ( rootport) and for unit under test  i used all bmd files instead of Pio files

4. i have changed pcie_2_0_rport_v6.v file such as AR33918

5.Replace the pci_exp_usrapp_cfg.v with the one that is included in the zip file in  AR33918

6.Call the task TSK_WRITE_CFG_DW in  testbench (AR33918)

board.RP.cfg_usrapp.TSK_WRITE_CFG_DW(32'h00000004, 32'h00000007, 4'b1110);

7. then i start to write the length , amount , address and finally start the Memory read Request test such as "dma_mrd_test".

 

vsim +notimingchecks -t 1ps +TESTNAME=dma_mrd_test -voptargs="+acc" -L work -L secureip -L unisims_ver \
    work.board glbl
run -all


Result

1. after starting the memory Read request ( mrd_start was set )  , BMD not sent any mermory read request.

please help me solve this problem.

the transcript result attached.

and "dma_mrd_test" is:


**************************************************************************************************************************
else if(testname == "dma_mrd_test")
begin


    TSK_SIMULATION_TIMEOUT(5050);

    //System Initialization
    TSK_SYSTEM_INITIALIZATION;

    TSK_BAR_INIT;



       
    $display("[%t] : Expected Device/Vendor ID = %x", $realtime, DEV_VEN_ID);
  

    //Read command reg
    $display("[%t] : Read Command Reg",$realtime);
    fork
    TSK_TX_TYPE0_CONFIGURATION_READ(DEFAULT_TAG,12'h04,4'hF);
    DEFAULT_TAG = DEFAULT_TAG + 1;
    TSK_WAIT_FOR_READ_DATA;
    join
    $display("[%t] :Command Reg Data is :%x", $realtime, P_READ_DATA);
   
    //Set the DMA(2) and Interrupt(10) bit in command
    P_READ_DATA = P_READ_DATA | 32'h0404;
    $display("[%t] :New Command Reg Data is :%x", $realtime, P_READ_DATA);

    //Write Command Reg
    $display("[%t] : Write Command Reg",$realtime);
    fork
    TSK_TX_TYPE0_CONFIGURATION_WRITE(DEFAULT_TAG,12'h04,P_READ_DATA[31:0],4'hF);
    DEFAULT_TAG = DEFAULT_TAG + 1;
    TSK_TX_CLK_EAT(100);
    join
   
    //--------------------------------------------------------------------------
    // Write DMA configuration
    //--------------------------------------------------------------------------

   
    $display("[%t] : Writing DCR1 With 0x01", $realtime);
    fork
    data=32'h01;
    DATA_STORE[0] = data[7:0];
    DATA_STORE[1] = data[15:8];
    DATA_STORE[2] = data[23:16];
    DATA_STORE[3] = data[31:24];

    TSK_TX_MEMORY_WRITE_32(DEFAULT_TAG, DEFAULT_TC,10'd1,BAR_INIT_P_BAR[0]+8'h0,4'b0,4'hF,1'b0);
    DEFAULT_TAG = DEFAULT_TAG + 1;
    TSK_TX_CLK_EAT(100);
    join
   
    $display("[%t] : Writing DCR1 With 0x00", $realtime);
    fork
    data=32'h0;
    DATA_STORE[0] = data[7:0];
    DATA_STORE[1] = data[15:8];
    DATA_STORE[2] = data[23:16];
    DATA_STORE[3] = data[31:24];

    TSK_TX_MEMORY_WRITE_32(DEFAULT_TAG, DEFAULT_TC,10'd1,BAR_INIT_P_BAR[0]+8'h0,4'b0,4'hF,1'b0);
    DEFAULT_TAG = DEFAULT_TAG + 1;
    TSK_TX_CLK_EAT(100);
    join

    $display("[%t] : Writing RDMATLPA", $realtime);
    fork
    data=0;
    DATA_STORE[0] = data[7:0];
    DATA_STORE[1] = data[15:8];
    DATA_STORE[2] = data[23:16];
    DATA_STORE[3] = data[31:24];

    TSK_TX_MEMORY_WRITE_32(DEFAULT_TAG, DEFAULT_TC,10'd1,BAR_INIT_P_BAR[0]+8'h1c,4'b0,4'hF,1'b0);
    DEFAULT_TAG = DEFAULT_TAG + 1;
    TSK_TX_CLK_EAT(100);
    join

    $display("[%t] : Writing RDMATLPS", $realtime);
    fork
    data=32'h20;//tlps;
    DATA_STORE[0] = data[7:0];
    DATA_STORE[1] = data[15:8];
    DATA_STORE[2] = data[23:16];
    DATA_STORE[3] = data[31:24];

    TSK_TX_MEMORY_WRITE_32(DEFAULT_TAG, DEFAULT_TC,10'd1,BAR_INIT_P_BAR[0]+8'h20,4'b0,4'hF,1'b0);
    DEFAULT_TAG = DEFAULT_TAG + 1;
    TSK_TX_CLK_EAT(100);
    join

    $display("[%t] : Writing RDMATLPC", $realtime);
    fork
    data=32'h10;//tlpc;
    DATA_STORE[0] = data[7:0];
    DATA_STORE[1] = data[15:8];
    DATA_STORE[2] = data[23:16];
    DATA_STORE[3] = data[31:24];

    TSK_TX_MEMORY_WRITE_32(DEFAULT_TAG, DEFAULT_TC,10'd1,BAR_INIT_P_BAR[0]+8'h24,4'b0,4'hF,1'b0);
    DEFAULT_TAG = DEFAULT_TAG + 1;
    TSK_TX_CLK_EAT(100);
    join

    $display("[%t] : Writing DCR2 With 0x00010000", $realtime);
    fork
    data=32'h00010000;
    DATA_STORE[0] = data[7:0];
    DATA_STORE[1] = data[15:8];
    DATA_STORE[2] = data[23:16];
    DATA_STORE[3] = data[31:24];

    TSK_TX_MEMORY_WRITE_32(DEFAULT_TAG, DEFAULT_TC,10'd1,BAR_INIT_P_BAR[0]+8'h04,4'b0,4'hF,1'b0);
    DEFAULT_TAG = DEFAULT_TAG + 1;
    TSK_TX_CLK_EAT(100);
    join
    $finish;
end
**************************************************************************************************************************

 

thank you very much,

armando.

 

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11 Replies
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Xilinx Employee
Xilinx Employee
8,708 Views
Registered: ‎08-06-2008

What is the status of cfg_command[2]?

It should be '1'.

 

Thanks,

DMS

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Observer
Observer
8,703 Views
Registered: ‎05-28-2011

Hi DMS,

the stutus of  cfg_command[2] is "1";

cfg_command = 0000 0100 0000 0111;

thanks for your helps.

armando.

 

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Observer
Observer
8,702 Views
Registered: ‎05-28-2011

Hi DMS,

excuse me,

I don't know the stutus of  cfg_command[2] is "1" or "0"

How can I change the value of cfg_command[2]?

thanks for your helps.

armando.

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Observer
Observer
8,696 Views
Registered: ‎05-28-2011

HI,

 I change the value of cfg_command[2] by AR33918 and all Read request received in RP from BMD application(TLP count is 16 and 16 read request TLP Receive in RP this is ok!) but the problem is hear: the completions not respond by RP and the end of transcript is below:

....

113410000] : TSK_PARSE_FRAME on Receive
# [           117770000] : Expected Device/Vendor ID = 000710ee
# [           117770000] : Read Command Reg
# [           117794000] : TSK_PARSE_FRAME on Transmit
# [           119210000] : TSK_PARSE_FRAME on Receive
# [           119218000] :Command Reg Data is :00100003
# [           119218000] :New Command Reg Data is :00100407
# [           119218000] : Write Command Reg
# [           119242000] : TSK_PARSE_FRAME on Transmit
# [           120018000] : Writing DCR1 With 0x01
# [           120042000] : TSK_PARSE_FRAME on Transmit
# [           120658000] : TSK_PARSE_FRAME on Receive
# [           120818000] : Writing DCR1 With 0x00
# [           120842000] : TSK_PARSE_FRAME on Transmit
# [           121618000] : Writing RDMATLPA
# [           121642000] : TSK_PARSE_FRAME on Transmit
# [           122418000] : Writing RDMATLPS
# [           122442000] : TSK_PARSE_FRAME on Transmit
# [           123218000] : Writing RDMATLPC
# [           123242000] : TSK_PARSE_FRAME on Transmit
# [           124018000] : Writing DCR2 With 0x00010000
# [           124042000] : TSK_PARSE_FRAME on Transmit
# [           127202000] : TSK_PARSE_FRAME on Receive
# [           127218000] : TSK_PARSE_FRAME on Receive
# [           127250000] : TSK_PARSE_FRAME on Receive
# [           127266000] : TSK_PARSE_FRAME on Receive
# [           127298000] : TSK_PARSE_FRAME on Receive
# [           127314000] : TSK_PARSE_FRAME on Receive
# [           127346000] : TSK_PARSE_FRAME on Receive
# [           127362000] : TSK_PARSE_FRAME on Receive
# [           127394000] : TSK_PARSE_FRAME on Receive
# [           127410000] : TSK_PARSE_FRAME on Receive
# [           127442000] : TSK_PARSE_FRAME on Receive
# [           127458000] : TSK_PARSE_FRAME on Receive
# [           128242000] : TSK_PARSE_FRAME on Receive
# [           128306000] : TSK_PARSE_FRAME on Receive
# [           128322000] : TSK_PARSE_FRAME on Receive
# [           128354000] : TSK_PARSE_FRAME on Receive
# [           148542000] : TEST FAILED --- Haven't Received All Expected TLPs
# ** Note: Data structure takes 239780928 bytes of memory
#          Process time 122.23 seconds
#          $finish    : ../dsport/pci_exp_usrapp_rx.v(303)
#    Time: 148542 ns  Iteration: 7  Instance: /board/RP/rx_usrapp
# 1
# Break in Module pci_exp_usrapp_rx at ../dsport/pci_exp_usrapp_rx.v line 303
# Simulation Breakpoint: 1
# Break in Module pci_exp_usrapp_rx at ../dsport/pci_exp_usrapp_rx.v line 303
# MACRO ./simulate_mti.do PAUSED at line 33

 

-------------------------------------------------------------------------

this is pci_exp_usrapp_rx.v line 297---304

always @(trn_clk or trn_rsof_n or trn_rsrc_rdy_n) begin
               
    if (next_trn_rx_timeout == 0) begin
        if(!`EXPECT_FINISH_CHECK)
          $display("[%t] : TEST FAILED --- Haven't Received All Expected TLPs", $realtime);

        $finish(2);<==line 303
    end

----------------------------------------------------------------------------

Thanks for your help again.

armando.

 

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Xilinx Employee
Xilinx Employee
8,691 Views
Registered: ‎04-06-2010

If you're using the Root Port example from the dsport directory, then the RP is not going to respond to completions.   The RP in this model is not intented to be mastered by the endpoint.  This is why the only tests it has are called PIO.

 

You can probably add this capability, but you're going to need to add this yourself.

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Observer
Observer
8,680 Views
Registered: ‎05-28-2011

HI,

but How can I add capabilty of respond completions to  RP to test my BMD design application?

and IS any source code to help me for this?

thanks for your help.

armando.

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Observer
Observer
8,672 Views
Registered: ‎05-28-2011

Hi all, How can I add capability of respond to read request in root port to test my BMD program? thanks. armando.
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Xilinx Employee
Xilinx Employee
8,667 Views
Registered: ‎04-06-2010

You're probably going to need to add a task in your rx_usrapp module that waits for the memory read request to come in.

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Visitor
Visitor
8,656 Views
Registered: ‎08-01-2011

Hi luisb,

What about those tasks TSK_EXPECT_MEMWR or TSK_EXPECT_MEMRD? I'm trying to use first one but always get message "TEST FAILED --- Haven't Received All Expected TLPs".
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Visitor
Visitor
3,629 Views
Registered: ‎04-11-2013

Hi, I meet the same problem now .And the bus master enable is set to 1.How you solve the problem? Thanks for your help.
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Visitor
Visitor
3,627 Views
Registered: ‎04-11-2013

Hi, I meet the same problem now .And the bus master enable is set to 1.How you solve the problem? Thanks for your help.
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