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omkarg
Visitor
Visitor
474 Views
Registered: ‎11-13-2019

magic_stopped C2H channel 0 status bit is set

Hello,

I am using the product for which following is the product guide - PG195 (v4.1) June 20, 2019 DMA/Bridge Subsystem for PCIe v4.1

I am doing Endpoint to Root Complex memory transaction. For the same I have defined the descriptors and enabled the descriptor mode for C2H transfer.

I have programmed the descriptor as per the details provided in the above mentioned PG. Yet I see 'magic_stopped' bit of the C2H channel 0 status register is set and I also have desc_error[4:0] of the same register as 0x1 which means "Unsupported request" as per the PG.

Please suggest a solution for the same

 

Regards,

Omkar

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liy
Xilinx Employee
Xilinx Employee
450 Views
Registered: ‎08-02-2007

would you please check the magic bit in the descriptor?

What is the value? This should be the one suggested in the PG

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omkarg
Visitor
Visitor
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Registered: ‎11-13-2019

The PG suggests 16'had4b for Magic[15:0] and I have programmed the Descriptor with the same value at the same bit locations.

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