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srikar900
Newbie
Newbie
354 Views
Registered: ‎02-05-2020

pci example error in vivado 2018.3

i am to IP core so i wanted to try the PCI example design in vivado 2018.3 but got this error, so tried in vivado 2017.4 it worked fine except i wanted to do on implementation on VC707 board but i was not able to implement the example design as the logic was not present in the design source,if there is any reference design which can be implemeted on VC707 board or in 7 series please share the design,just wanted to transfer the data through pci using ip core but couldn't find any solution .   

2018.3 pci error.png

 

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garethc
Moderator
Moderator
304 Views
Registered: ‎06-29-2011

Hi @srikar900 

If you execute the following command after getting the error with the example design project. This will create the BRAM controller using v4.1 IP. 

 
create_ip -name axi_bram_ctrl -version 4.1 -vendor xilinx.com -library ip -module_name axi_bram_ctrl_0
set_property -dict [list CONFIG.DATA_WIDTH {64} CONFIG.ID_WIDTH {4} CONFIG.PROTOCOL {AXI4} CONFIG.SUPPORTS_NARROW_BURST {0} CONFIG.SINGLE_PORT_BRAM {1} CONFIG.USE_ECC {0} CONFIG.FAULT_INJECT {0} CONFIG.ECC_ONOFF_RESET_VALUE {0} CONFIG.BMG_INSTANCE {INTERNAL} CONFIG.MEM_DEPTH {2048}] [get_ips axi_bram_ctrl_0]
 
generate_target all [get_ips *]

Thanks,

Gareth


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srikar900
Newbie
Newbie
277 Views
Registered: ‎02-05-2020

thank you gareth for the reply but after implementating i am not seeing any data transfer in the debug module is there any drivers like MET driver which generate traffic for virtex 7 boards and windows os ,all i find are linux drivers.

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