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Observer filmil
Observer
8,199 Views
Registered: ‎08-15-2007

"*dcm_i" not found when generating the example design for PCIe Endpoint Block

Hello.

I am trying to generate the example design for the PCI Express Endpoint Block 1.4 (comes with ISE 9.1.03i).  I use SynplifyPro 8.8.0.4 for synthesis.  The board is HTG-V5-PCIE-50T.  The completer in the example design as generated by CoreGen is in a NGC file.

Upon synthesis, I get the following message:
Applying constraints in "htg-v5-pcie.ucf" to the design...
ERROR:NgdBuild:752 - "htg-v5-pcie.ucf" Line 39: Could not find instance(s)
   '*dcm_i' in the design.  To suppress this error, specify the correct instance
   name or remove the constraint.  The 'Allow Unmatched LOC Constraints' ISE
   property can also be set ( -aul switch for command line users ).
ERROR:Parsers:11 - Encountered unrecognized constraint while parsing.
ERROR:NgdBuild:19 - Errors found while parsing constraint file
   "htg-v5-pcie.ucf".
(see the UCF file below)

If I uncomment the constraint for NET "*dcm_i", I get a design that fails the 1.2ns timing constraints given below.  Is there a way out?

# UCF for numlanes:8; part:lx50t; package:ff1136

####################################################################
#
# Begin specs common to all devices
#
####################################################################

# Timing specifications common to all board/chip

# This constraint is unused on the HTG board.
#  NET "*_clk"             PERIOD = 4ns;


# MAXDELAY delay constraints to meet timing from pcie to flop
 
NET "*pipe_tx_data_l*"                   MAXDELAY = 1.8 ns;
NET "*pipe_tx_data_k_l*"                 MAXDELAY = 1.8 ns;
NET "*pipe_tx_detect_rx_loopback_l*"     MAXDELAY = 1.8 ns;
NET "*pipe_tx_compliance_l*"             MAXDELAY = 1.8 ns;
NET "*pipe_rx_polarity_l*"               MAXDELAY = 1.8 ns;
NET "*pipe_power_down_l*"                MAXDELAY = 1.8 ns;
NET "*pipe_reset_l*"                     MAXDELAY = 1.8 ns;
NET "*pipe_tx_elec_idle_l*"              MAXDELAY = 1.8 ns;

# MAXDELAY delay constraints to meet 250 MHz timing on user_clk

NET "*llk_rx_data*"                      MAXDELAY = 1.2 ns;
NET "*llk_rx_src_last_req_n*"            MAXDELAY = 1.2 ns;
NET "*llk_rx_valid_n*"                   MAXDELAY = 1.2 ns;
NET "*llk_tc_status*"                    MAXDELAY = 1.2 ns;

# PLL specification

  INST "*/pcie_clocking_i/use_pll.pll_i" LOC = PLL_ADV_X0Y2;

# DCM specification

 INST "*dcm_i"         LOC = DCM_ADV_X0Y5;

# end specs common to all board/chip


####################################################################
#
# Begin part/package specific assignments
#
####################################################################
# Clock pins that drive the GT connected to lane 2 and 3

# GT locations: Placement for the HTG board
 
INST  "*/GTD?0*GT_i" LOC = GTP_DUAL_X0Y3; 
INST  "*/GTD?2*GT_i" LOC = GTP_DUAL_X0Y2; 
INST  "*/GTD?4*GT_i" LOC = GTP_DUAL_X0Y1; 
INST  "*/GTD?6*GT_i" LOC = GTP_DUAL_X0Y0;

# Reference Design BRAM/Slice locations

  INST "*completer/mem/*" AREA_GROUP = completer_machine;
  INST "*completer/I0/*" AREA_GROUP = completer_machine;

  AREA_GROUP "completer_machine" RANGE = RAMB36_X1Y4:RAMB36_X1Y7;
  AREA_GROUP "completer_machine" RANGE = SLICE_X17Y46:SLICE_X59Y26;

####################################################################
#
# Begin board specific pin assignments
#
####################################################################

# Header Pins

# 250 MHz TXCLKOUT0 from the GT used for Lane0
#  NET "TXCLKOUT"          LOC = ;  

# REFCLKOUT from the GT used for Lane0. The frequency is equal to the
# frequency of reference clock selected
#  NET "REFCLKOUT"         LOC = ; 

# PLLLKDET from the GT used for Lane0. Indicates if the GT PLL is locked
#  NET "PLLLKDETOUT"       LOC = ;

# 250 Mhz Clock
#  NET "CORECLK"           LOC = ;

# Frequency of the USERCLK depends on the CLK RATIO selected.
# 1:1 - 250 Mhz ; 1:2 - 125 Mhz ; 1:4 - 62.5 Mhz
#  NET "USERCLK"           LOC = "";


# Leds
# Indicates that the PCIe endpoint has successfully completed link training
# with the downstream port connected to it
# NET "LINKUP"            LOC = "F26"; 

# Indicates  the PLL used to generate the core clk and user clk is locked
# NET "CLKLOCK"           LOC = "F25";


# Push Buttons 
# Reset to the PCIe block, should be connected to the system reset
# NET RST_N               LOC = "G27";
# NET RST_N PULLUP;

# Reset to the GT?_DUAL tile
# NET GTRESET_N          LOC = "G27";
# NET GTRESET_N PULLUP;


##*** User Interface User Resest, DIP Switches, System Clock, and LED's
NET "USR_RESET" LOC ="G27";
NET "USR_RESET" PULLUP;
NET "USRCLK" LOC ="J16";
NET "LED7" LOC ="F26";
NET "LED6" LOC ="F25";
NET "LED5" LOC ="H24";
NET "LED4" LOC ="H25";
NET "LED3" LOC ="G26";
NET "LED2" LOC ="G25";
NET "LED1" LOC ="J26";
NET "LED0" LOC ="J27";

#*** PCIe MGT Receiver Interface
NET "PET7_P" LOC ="AP3";
NET "PET7_N" LOC ="AP2";
NET "PET6_P" LOC ="AL1";
NET "PET6_N" LOC ="AM1";
NET "PET5_P" LOC ="AH1";
NET "PET5_N" LOC ="AG1";
NET "PET4_P" LOC ="AE1";
NET "PET4_N" LOC ="AF1";
NET "PET3_P" LOC ="AB1";
NET "PET3_N" LOC ="AA1";
NET "PET2_P" LOC ="W1";
NET "PET2_N" LOC ="Y1";
NET "PET1_P" LOC ="T1";
NET "PET1_N" LOC ="R1";
NET "PET0_P" LOC ="N1";
NET "PET0_N" LOC ="P1";

#*** PCIe MGT Transmitter Interface
NET "PER7_P" LOC ="AN4";
NET "PER7_N" LOC ="AN3";
NET "PER6_P" LOC ="AK2";
NET "PER6_N" LOC ="AL2";
NET "PER5_P" LOC ="AJ2";
NET "PER5_N" LOC ="AH2";
NET "PER4_P" LOC ="AD2";
NET "PER4_N" LOC ="AE2";
NET "PER3_P" LOC ="AC2";
NET "PER3_N" LOC ="AB2";
NET "PER2_P" LOC ="V2";
NET "PER2_N" LOC ="W2";
NET "PER1_P" LOC ="U2";
NET "PER1_N" LOC ="T2";
NET "PER0_P" LOC ="M2";
NET "PER0_N" LOC ="N2";

#*** PCIe MGT Clock Interface
NET "PCIECLK0_P" LOC ="Y4";
NET "PCIECLK0_N" LOC ="Y3";

# End UCF for numlanes:8; part:lx50t; package:ff1136
f

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1 Reply
Observer filmil
Observer
8,168 Views
Registered: ‎08-15-2007

Re: "*dcm_i" not found when generating the example design for PCIe Endpoint Block

FWIW, I determined that the "*dcm_i" constraint need not be used.  The remaining timing issues were solved by placing the problematic cells by hand.

f

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