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314 Views
Registered: ‎10-17-2019

setup time violation

Hi 

If i am getting setup time violations in my design so how i can resolve it?

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10 Replies
312 Views
Registered: ‎06-21-2017

Re: setup time violation

Make your design faster or use a slower clock. 

If you need more detail, supply more information about your design and the timing problems.

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243 Views
Registered: ‎10-17-2019

Re: setup time violation

If i dont want to move on slower clock?

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238 Views
Registered: ‎06-21-2017

Re: setup time violation

Thebn you need to do something to make the design run faster.  You have not provided enough information to give any more advise.  The timing report would be a good start.  What part?  What design language?

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211 Views
Registered: ‎10-17-2019

Re: setup time violation

hi,

actually generally i am asking this i dont have any design. 

And in case CDC if wan to sample a pulse from higher clock to lower clock domain then you know we need to streatch the clock enough to get sampled in lower clock domian.

So where we have to write that logic that is  in Lower clock domain and could you please tell me how to do that?

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189 Views
Registered: ‎06-21-2017

Re: setup time violation

You will need to stretch the pulse in the faster clock domain.  You can do this with a couple registers and an OR gate.  Draw a picture.  This isn't hard to code.  If the clocks are derived from a common oscillator, this may be enough.  If not, or if you are getting timing errors, you need to write some code to do the clock domain crossing.  Search these forums for CDC.  You will get several pages of results.

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137 Views
Registered: ‎10-17-2019

Re: setup time violation

instead to run your design faster is there any another way to resolve setup time violation?

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Mentor watari
Mentor
126 Views
Registered: ‎06-16-2013

Re: setup time violation

Hi kumar090192@gmail.com 

 

Change the strategy.

Refe the following URL.

 

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2019_1/ug904-vivado-implementation.pdf

 

Also, the following URL is helpful for you, if you have setup timing violation issue.

 

https://www.xilinx.com/products/design-tools/ultrafast.html

 

Best regards,

Participant aforencich
Participant
90 Views
Registered: ‎08-14-2013

Re: setup time violation

To synchronize a pulse, you need to use a pulse synchronizer. If the time between pulses is large, then you can simply convert the pulse to a level change (toggle on pulse), sync that, and edge detect it to get pulses in the dest clock domain. If the pulses can be close enough together that this won't work, the you can use the pulses to increment a gray counter, sync that, and then use another gray counter to compare and regenerate the pulses, similar to how the gray coded pointers work in async FIFO designs.
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87 Views
Registered: ‎10-17-2019

Re: setup time violation

okay and in case asynchronous FIFO how we handle the full and empty signals as there are two clocks one for read and one for write?

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Participant aforencich
Participant
74 Views
Registered: ‎08-14-2013

Re: setup time violation

Generally the full signal is used on the write side and the empty signal is used on the read side, so presumably they will be generated in the appropriate clock domain. Alternatively, you could have a FIFO module that doesn't present full and empty signals, instead presenting a full AXI stream interface or similar.
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