12-09-2019 07:09 AM
Make your design faster or use a slower clock.
If you need more detail, supply more information about your design and the timing problems.
12-10-2019 04:16 AM
Thebn you need to do something to make the design run faster. You have not provided enough information to give any more advise. The timing report would be a good start. What part? What design language?
12-10-2019 08:48 PM
actually generally i am asking this i dont have any design.
And in case CDC if wan to sample a pulse from higher clock to lower clock domain then you know we need to streatch the clock enough to get sampled in lower clock domian.
So where we have to write that logic that is in Lower clock domain and could you please tell me how to do that?
12-11-2019 04:35 AM
You will need to stretch the pulse in the faster clock domain. You can do this with a couple registers and an OR gate. Draw a picture. This isn't hard to code. If the clocks are derived from a common oscillator, this may be enough. If not, or if you are getting timing errors, you need to write some code to do the clock domain crossing. Search these forums for CDC. You will get several pages of results.
12-15-2019 11:12 PM
Change the strategy.
Refe the following URL.
Also, the following URL is helpful for you, if you have setup timing violation issue.
12-16-2019 08:51 PM
12-16-2019 08:58 PM
okay and in case asynchronous FIFO how we handle the full and empty signals as there are two clocks one for read and one for write?
12-16-2019 09:54 PM