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Visitor
Visitor
3,764 Views
Registered: ‎05-18-2010

simulation problem with PCI EXPRESS endpoint_pipe v1.7-help???!!

I have used the modelsim se6.1b+ISE 10.1webpack to do the simulation of PCI-E endpoint_pipe v1.7 example design,the fault occer:

              cd C:/coregen/endpoint_pipe/simulation/functional
do C:/coregen/endpoint_pipe/simulation/functional/simulate_mti.do
# ** Warning: (vlib-34) Library already exists at "work".
# Reading C:\Modeltech_6.1b\win32/../modelsim.ini
# "work" maps to directory work. (Default mapping)
# Model Technology ModelSim SE vlog 6.1b Compiler 2005.09 Sep  8 2005
# ** Warning: (vlog-2103) Directory "C:\Xilinx\10.1\ISE/smartmodel/lin/wrappers/mtiverilog" for -y option not found.
# -- Compiling module px1011a
# -- Compiling module boardx01
# -- Compiling module sys_clk_gen
# -- Compiling module sys_clk_gen_ds
# -- Compiling module xilinx_pci_exp_1_lane_epipe_ep
# -- Compiling module endpoint_pipe
# -- Compiling module glbl
# -- Compiling module pci_exp_32b_app
# -- Compiling module PIO_EP
# -- Compiling module PIO_EP_MEM_ACCESS
# -- Compiling module EP_MEM
# -- Compiling module PIO_32_RX_ENGINE
# -- Compiling module PIO_32_TX_ENGINE
# -- Compiling module PIO_TO_CTRL
# -- Compiling module PIO
# -- Compiling module xilinx_pci_exp_1_lane_downstream_port
# -- Compiling module xilinx_pci_exp_1_lane_dsport
# -- Compiling module dsport_cfg
# -- Compiling module pci_exp_usrapp_rx
# -- Compiling module pci_exp_usrapp_tx
# -- Compiling module pci_exp_usrapp_com
# -- Compiling module pci_exp_usrapp_cfg
# -- Compiling module pci_exp_1_lane_64b_dsport
# -- Scanning library directory 'C:\Xilinx\10.1\ISE/verilog/src/simprims'
# -- Scanning library directory 'C:\Xilinx\10.1\ISE/verilog/src/unisims'
# -- Compiling module OBUF
# -- Compiling module IBUF
# -- Compiling module VCC
# -- Compiling module GND
# -- Compiling module INV
# -- Compiling module FD
# -- Compiling module SRL16
# -- Compiling module FDE
# -- Compiling module SRL16E
# -- Compiling module LUT4_L
# -- Compiling module LUT4_D
# -- Compiling module LUT3_L
# -- Compiling module LUT3_D
# -- Compiling module LUT2_D
# -- Compiling module LUT2_L
# -- Compiling module MUXF5
# -- Compiling module LUT2
# -- Compiling module LUT3
# -- Compiling module LUT4
# -- Compiling module FDP
# -- Compiling module FDR
# -- Compiling module BUF
# -- Compiling module LUT1
# -- Compiling module FDRSE
# -- Compiling module FDRE
# -- Compiling module FDCE
# -- Compiling module FDRS
# -- Compiling module FDS
# -- Compiling module MUXF6
# -- Compiling module MUXCY
# -- Compiling module XORCY
# -- Compiling module FDSE
# -- Compiling module SRLC16E
# -- Compiling module RAMB16_S9_S9
# -- Compiling module FDPE
# -- Compiling module FDC
# -- Compiling module RAM16X1D
# -- Compiling module FDDRCPE
# -- Compiling module BUFG
# -- Compiling module DCM
# -- Compiling module dcm_clock_divide_by_2
# -- Compiling module dcm_maximum_period_check
# -- Compiling module dcm_clock_lost
# -- Compiling module RAMB16_S36_S36
# -- Compiling module GT11CLK_MGT
# -- Compiling module LUT1_L
# -- Compiling module DCM_ADV
# -- Compiling module dcm_adv_clock_divide_by_2
# -- Compiling module dcm_adv_maximum_period_check
# -- Compiling module dcm_adv_clock_lost
# -- Compiling module MUXCY_L
# -- Compiling module SRLC16
# -- Compiling module GT11
# -- Compiling module MULT_AND
# -- Compiling module RAMB16_S18_S18
# -- Scanning library directory 'C:\Xilinx\10.1\ISE/verilog/src/simprims'
# -- Scanning library directory 'C:\Xilinx\10.1\ISE/verilog/src/unisims'
#
# Referenced (but uncompiled) modules or primitives:
#  GT11_SWIFT
#
# Top level modules:
#  boardx01
#  glbl
# vsim +notimingchecks +TESTNAME=sample_smoke_test0 -L work work.boardx01 glbl
# Loading work.boardx01
# Loading work.px1011a
# Loading work.xilinx_pci_exp_1_lane_epipe_ep
# Loading work.OBUF
# Loading work.IBUF
# Loading work.pci_exp_32b_app
# Loading work.PIO
# Loading work.PIO_EP
# Loading work.PIO_EP_MEM_ACCESS
# Loading work.EP_MEM
# Loading work.RAMB16_S36_S36
# Loading work.PIO_32_RX_ENGINE
# Loading work.PIO_32_TX_ENGINE
# Loading work.PIO_TO_CTRL
# Loading work.endpoint_pipe
# Loading work.VCC
# Loading work.GND
# Loading work.INV
# Loading work.FD
# Loading work.SRL16
# Loading work.FDE
# Loading work.SRL16E
# Loading work.LUT4_L
# Loading work.LUT4_D
# Loading work.LUT3_L
# Loading work.LUT3_D
# Loading work.LUT2_D
# Loading work.LUT2_L
# Loading work.MUXF5
# Loading work.LUT2
# Loading work.LUT3
# Loading work.LUT4
# Loading work.FDP
# Loading work.FDR
# Loading work.BUF
# Loading work.LUT1
# Loading work.FDRSE
# Loading work.FDRE
# Loading work.FDCE
# Loading work.FDRS
# Loading work.FDS
# Loading work.MUXF6
# Loading work.MUXCY
# Loading work.XORCY
# Loading work.FDSE
# Loading work.SRLC16E
# Loading work.RAMB16_S9_S9
# Loading work.FDPE
# Loading work.FDC
# Loading work.RAM16X1D
# Loading work.FDDRCPE
# Loading work.BUFG
# Loading work.DCM
# Loading work.xilinx_pci_exp_1_lane_downstream_port
# Loading work.xilinx_pci_exp_1_lane_dsport
# Loading work.GT11CLK_MGT
# Loading work.pci_exp_1_lane_64b_dsport
# Loading work.LUT1_L
# Loading work.DCM_ADV
# Loading work.dcm_adv_clock_divide_by_2
# Loading work.dcm_adv_maximum_period_check
# Loading work.dcm_adv_clock_lost
# Loading work.MUXCY_L
# Loading work.SRLC16
# Loading work.GT11
# ** Error: (vsim-3033) C:/Xilinx/10.1/ISE/verilog/src/unisims/GT11.v(2563): Instantiation of 'GT11_SWIFT' failed. The design unit was not found.
#         Region: /boardx01/xilinx_pci_exp_1_lane_downstream_port/xilinx_pci_exp_1_lane_dsport/pci_exp_1_lane_64b_dsport/plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST
#         Searched libraries:
#             work
#             work
# ** Error: (vsim-3033) C:/Xilinx/10.1/ISE/verilog/src/unisims/GT11.v(2563): Instantiation of 'GT11_SWIFT' failed. The design unit was not found.
#         Region: /boardx01/xilinx_pci_exp_1_lane_downstream_port/xilinx_pci_exp_1_lane_dsport/pci_exp_1_lane_64b_dsport/plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2
#         Searched libraries:
#             work
#             work
# Loading work.MULT_AND
# Loading work.RAMB16_S18_S18
# Loading work.dsport_cfg
# Loading work.pci_exp_usrapp_rx
# Loading work.pci_exp_usrapp_tx
# Loading work.pci_exp_usrapp_cfg
# Loading work.pci_exp_usrapp_com
# Loading work.sys_clk_gen_ds
# Loading work.sys_clk_gen
# Loading work.glbl
# Error loading design
# Error: Error loading design
#        Pausing macro execution
# MACRO C:\coregen\endpoint_pipe\simulation\functional\simulate_mti.do PAUSED at line 8

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Xilinx Employee
Xilinx Employee
3,755 Views
Registered: ‎04-06-2010

Do you know if you compiled your libraries for Modelsim?

You should see them in your Libraries tab.

The Libraries that you should see is the "secureip" and "unisims_ver" libraries.

If you have them compiled, then you need to make sure that your vsim command uses these libraries. 

You'll need to add the following to you vsim command:

 

-L unisims_ver

-L secureip

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