why one pcie ip only for limited boards

[sf]

Hi,

I am quite new to xilinx ip. I am trying to find a proper pcie ip for my project. I notice there are several pcie ips for different fpga boards. I am confused here why one pcie ip only supports limited types of boards. My understanding is I will program the ip onto a board, so as far as the board has enough resources for the ip, the ip should be compatible with that board.  Can someone help clarify my confusion? I guess it's a stupid question but I haven't found the answer.

[pvenugo · Accepted solution]

Hi @sf ,

It depends on the type of board if it has a PCIe finger would be able to use PCIe IP core and route it through the finger on board.

Otherwise, user have to use FMC based PCIe connector to extend to endpoint.

User will have flexibility to choose as per the requirement.

Regards

Praveen

[sf]

Hi pvenugo,

Thank you, it makes sense. One more question, I understand whether boards have pcie finger influences how the pcie ip is connected to the board now. But does that also influence the rtl design of the ip? I am not familiar to the difference between pcie finger and FMC. I am guessing the pin connection is different, as a result, the ports of the top module can be slightly different. But the core RTL design is not necessary to be different. Am I right? If there are more differences than I expect, it can be very helpful if you could give some examples.