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linux_carrier
Visitor
Visitor
1,573 Views
Registered: ‎04-02-2018

zcu102 pcie module basic questions

 I have some questions about the ZCU102 PCIe module:

 

(1). as in the picture(ug1085 Figure30-1: Block Diagram of the Controller for PCIe), what does Egress Address Translation/BAR and Ingress Address Translation/BAR work for?

Does those modules play the same role as BARs in the PCIe Spec?

 

(2). It has a Configuration/Status Register Block  which you can use for configing Integrated Block for PCIe Block

But here is what confuses me:

since you also can config Integrated Block for PCIe Block through ECAM in the AXI-PCIe Bridge Block, does that mean the two block functions is repeatable ? or Am I wrong?

 

pcie.PNG
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2 Replies
deepeshm
Xilinx Employee
Xilinx Employee
1,508 Views
Registered: ‎08-06-2008

Hi,

 

(1). as in the picture(ug1085 Figure30-1: Block Diagram of the Controller for PCIe), what does Egress Address Translation/BAR and Ingress Address Translation/BAR work for? Does those modules play the same role as BARs in the PCIe Spec?

Ans: We have two address domains here: AXI and PCIe. Those two blocks translate the address between PCIe and AXI  domains.
 
(2). It has a Configuration/Status Register Block  which you can use for configing Integrated Block for PCIe Block。

But here is what confuses me: since you also can config Integrated Block for PCIe Block through ECAM in the AXI-PCIe Bridge Block, does that mean the two block functions is repeatable ? or Am I wrong?

Ans: The APB interface configuration control is to set different attributes of the block. Please refer to UG1085. I have copied below the relevant section from the UG:

Configuration Control (APB Interface)

The attributes for the integrated block for PCIe (Endpoint or Root Port mode) are  configured through the programmable configuration and status registers (CSR) accessible  through the APB interface. APB interface uses the apb_clk, which is asynchronous to the  other clocks. It is a 32-bit wide address and 32-bit wide data bus interface.

The integrated block for PCIe attributes are used to set up the mode of operation (Root Port  or Endpoint), the list of capabilities and address pointers and so on. A detailed list of these  attributes is available in the PCIE_ATTRIB register set in the Zynq UltraScale+ MPSoC Register Reference (UG1087) [Ref 4].

ECAM is for generating configuration transactions for e.g. if you are reading a configuration space register from a downstream link partner.

Below is from UG1085:

Enhanced Configuration Access Mechanism

The bridge implements ECAM to translate AXI read or write transactions to PCIe configuration read or write TLPs. ECAM maps a portion of the AXI memory address space to  the PCI Express configuration transactions. A write transaction targeting this region is converted into a PCI Express configuration write transaction and a read transaction targeting this region is converted into a PCI Express configuration read transaction.

 

Thanks.

492 Views
Registered: ‎09-20-2019

I have configured INGRESS translation and it works properly from my windows driver i can read and write registers in the endpoint.

For the PCIe DMA I think I have to configure the EGRESS address translation. Someone can tell me what values do I have to set in source and destination registers? The 0xE000_0000 address (from address mapping PCIe) must be set in the destination?
What about the source address?


Many thanks for your support

 

Nicola

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