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Visitor kosmovirus
Visitor
6,066 Views
Registered: ‎03-31-2010

Problems simulating PicoBlaze KCPSM3 in Xilinx 11.1 and ModelSim SE

This is my first topic, so please be gentle but nevertheless point out my mistakes so i would not make them next time.

 

So... this is my problem.

I am trying to simulate the Picoblaze KCPSM3. I'm using the standard configuration (the VERILOG version) of the softcore, nothing added, nothing subtracted. The .psm file for the program ROM looks like this :  

 

 

ADDRESS 000

BEGIN:
 INPUT s0, 00
 AND  s0, 01
 JUMP END
END: 
 OUTPUT s0, 00
 JUMP BEGIN

 

So nothing complicated there. I have to mention that the problem is NOT with the KCPSM3 functionality.

I had the entire project made in Xilinx v11.1 and with it i had made a file witch stands as the testbench like is shown below. 

 

  

`timescale 1ns/100ps

module testbench;
 
// signals to connect kcpsm3_int_test


wire[7:0] port_id;
wire  write_strobe;
wire  read_strobe;
wire[7:0] out_port;
reg[7:0]  in_port;
reg  interrupt;
wire  interrupt_ack;
reg  reset;
reg  clk;

// Define the unit under test

 embedded_kcpsm3 uut(
 port_id,
 write_strobe,
 read_strobe,
 out_port,
 in_port,
 interrupt,
 interrupt_ack,
 reset,
 clk);


// Test Bench begins
 
  // Nominal 50MHz clock which also defines number of cycles in simulation


   parameter PERIOD = 20;

   always begin
      clk = 1'b0;
      #(PERIOD/2) clk = 1'b1;
      #(PERIOD/2);
   end 

initial
 begin
  reset <= 1'b0; in_port <= 8'b0000;
  #(PERIOD) reset <= 1'b1;
      #(30*PERIOD) in_port <= 8'b0001;
  #(PERIOD) in_port <= 8'b0010;
  #(67*PERIOD) in_port <= 8'b0011;
  #(PERIOD) in_port <= 8'b0100; 
  #(30*PERIOD) in_port <= 8'b0101;
  #(PERIOD) in_port <= 8'b0110;
  #(20*PERIOD);
    end

endmodule

 

OK ... That been said let's get to the actual problem.

I have selected the " Behavioral Simulation " enviroment and ofcourse started to  " Simulate Behavioral Model ". The ModelSim SE eviroment opened up with the work library initiated / created in Xilinx. So, the next step for me was to simulate the behavior. I selected the " Start Simulation ... " option from the Simulate menu in Model Sim. Selected the testbench file. UNCHECKED the "Enable Optimization " box (no other changes in the configuration project have been made until then).

 And after this step, these are the messages that appear :

 

 

# Top level modules:
#  kcpsm3
# Model Technology ModelSim SE vlog 6.2c Compiler 2006.08 Aug 26 2006
# -- Compiling module draft2
#
# Top level modules:
#  draft2
# Model Technology ModelSim SE vlog 6.2c Compiler 2006.08 Aug 26 2006
# -- Compiling module embedded_kcpsm3
#
# Top level modules:
#  embedded_kcpsm3
# Model Technology ModelSim SE vlog 6.2c Compiler 2006.08 Aug 26 2006
# -- Compiling module testbench
#
# Top level modules:
#  testbench
# Model Technology ModelSim SE vlog 6.2c Compiler 2006.08 Aug 26 2006
# -- Compiling module glbl
#
# Top level modules:
#  glbl
# vsim -L xilinxcorelib_ver -L unisims_ver -L unimacro_ver -lib work -t 1ps testbench glbl
# ** Note: (vsim-3812) Design is being optimized...
# ** Error: (vopt-19) Failed to access library 'xilinxcorelib_ver' at "xilinxcorelib_ver".
# No such file or directory. (errno = ENOENT)
# Error loading design
# Error: Error loading design
#        Pausing macro execution
# MACRO ./testbench.fdo PAUSED at line 10
vsim -L xilinxcorelib_ver -L unisims_ver -L unimacro_ver -lib work -t 1ps -novopt work.testbench
# vsim -L xilinxcorelib_ver -L unisims_ver -L unimacro_ver -lib work -t 1ps -novopt work.testbench
# Refreshing work.testbench
# Loading work.testbench
# ** Error: (vsim-19) Failed to access library 'xilinxcorelib_ver' at "xilinxcorelib_ver".
# No such file or directory. (errno = ENOENT)
# ** Error: (vsim-19) Failed to access library 'unisims_ver' at "unisims_ver".
# No such file or directory. (errno = ENOENT)
# ** Error: (vsim-19) Failed to access library 'unimacro_ver' at "unimacro_ver".
# No such file or directory. (errno = ENOENT)
# Refreshing work.embedded_kcpsm3
# Loading work.embedded_kcpsm3
# ** Warning: (vsim-3009) [TSCALE] - Module 'embedded_kcpsm3' does not have a `timescale directive in effect, but previous modules do.
#         Region: /testbench/uut
# ** Error: (vsim-19) Failed to access library 'xilinxcorelib_ver' at "xilinxcorelib_ver".
# No such file or directory. (errno = ENOENT)
# ** Error: (vsim-19) Failed to access library 'unisims_ver' at "unisims_ver".
# No such file or directory. (errno = ENOENT)
# ** Error: (vsim-19) Failed to access library 'unimacro_ver' at "unimacro_ver".
# No such file or directory. (errno = ENOENT)
# Refreshing work.kcpsm3
# Loading work.kcpsm3
# ** Error: (vsim-19) Failed to access library 'xilinxcorelib_ver' at "xilinxcorelib_ver".
# No such file or directory. (errno = ENOENT)
# ** Error: (vsim-19) Failed to access library 'unisims_ver' at "unisims_ver".
# No such file or directory. (errno = ENOENT)
# ** Error: (vsim-19) Failed to access library 'unimacro_ver' at "unimacro_ver".
# No such file or directory. (errno = ENOENT)
# ** Error: (vsim-3033) kcpsm3.v(404): Instantiation of 'LUT1' failed. The design unit was not found.
#         Region: /testbench/uut/processor
#         Searched libraries:
# ** Error: (vsim-19) Failed to access library 'xilinxcorelib_ver' at "xilinxcorelib_ver".
# No such file or directory. (errno = ENOENT)
# ** Error: (vsim-19) Failed to access library 'unisims_ver' at "unisims_ver".
# No such file or directory. (errno = ENOENT)
# ** Error: (vsim-19) Failed to access library 'unimacro_ver' at "unimacro_ver".
# No such file or directory. (errno = ENOENT)
#             work
# ** Error: (vsim-19) Failed to access library 'xilinxcorelib_ver' at "xilinxcorelib_ver".
# No such file or directory. (errno = ENOENT)
# ** Error: (vsim-19) Failed to access library 'unisims_ver' at "unisims_ver".
# No such file or directory. (errno = ENOENT)
# ** Error: (vsim-19) Failed to access library 'unimacro_ver' at "unimacro_ver".
# No such file or directory. (errno = ENOENT)
# ** Error: (vsim-3033) kcpsm3.v(410): Instantiation of 'FDR' failed. The design unit was not found.
#         Region: /testbench/uut/processor
#         Searched libraries:
# ** Error: (vsim-19) Failed to access library 'xilinxcorelib_ver' at "xilinxcorelib_ver".
# No such file or directory. (errno = ENOENT)
# ** Error: (vsim-19) Failed to access library 'unisims_ver' at "unisims_ver".
# No such file or directory. (errno = ENOENT)
# ** Error: (vsim-19) Failed to access library 'unimacro_ver' at "unimacro_ver".
# No such file or directory. (errno = ENOENT)
#             work

 

And much more similar to these above. OK! This was the first thing i did.

The second thing. I have selected the xcs500e-5fg320 design in Xilinx ISE and started "Compile HDL Simulation Libraries"

And this was the message :

 

Processing command line ...
Reading the compxlib configuration file - 'compxlib.cfg' ...
Library Source Paths => 'C:/Xilinx/11.1/ISE'
Current Working Directory => 'C:\Documents and Settings\murphy\Desktop\WORK\draft2'
Compilation Mode = FAST
Execute Mode = ON
Scheduling library installation & compilation for architectures: spartan3e

Scheduling library installation & compilation for libraries: simprim unisim xilinxcorelib edk

Signature:-
------------------------------------------------------------------------------
C:\Xilinx\11.1\ISE\bin\nt\unwrapped\compxlib.exe -s mti_se -l verilog -p C:/Modeltech_6.2c/win32 -arch spartan3e -lib unisim -lib simprim -lib xilinxcorelib -lib edk -exclude_deprecated -intstyle ise
------------------------------------------------------------------------------
ERROR:Compxlib - Compxlib does not support mti_se version 6.4a or prior releases. Parsing through the path setting on your system we have identified that you are using mti_se '6.2c'.
Please contact Mentor Graphics to upgrade to a supported simulator version. If the path setting is incorrect, please ensure that you are pointing to the latest version and re-invoke compxlib.
The list of supported simulator versions are listed in the Simulation Chapter of the Synthesis and Simulation Design Guide on
http://www.xilinx.com.
Simulator 'mti_se' is ignored.

Process "Compile HDL Simulation Libraries" failed

 

 

So these are the info that i have :

Xilinx ISE 11.1

ModelSIM SE PLUS 6.2c

The ModelSIM was installed separately from the Xilinx products.

 

I have tried to find the libraries that the ModelSIM mentions in the error log, but i could not find them. Anyone can help me on that ?

Or there is another way to simulate the functionality of the KCPSM3 in Xilinx or ModelSIM ?

 

Where do i go wrong ?

 

Please reply as quick as you can.

Thanks and have a nice day !

 

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1 Reply
Advisor eilert
Advisor
5,986 Views
Registered: ‎08-14-2007

Re: Problems simulating PicoBlaze KCPSM3 in Xilinx 11.1 and ModelSim SE

Hi ,

from reading the eror messages you have two choices:

Either update your Modelsim to a version above 6.4 to make   compxlib work.

  -- probably too expensive

 

Or compile the libraries manually.

You will find the sources in your Xilinx base path under:

>XILINX_PATH</ISE/verilog/src/...

 

 There are several subdirectories that contain the library sources.

Create a project in Modelsim.

Create the libraries and mappings. (VLIB, VMAP)

compile the sources to these libraries.  (see the compiler options how to choose the target library, don't compile to work, that won't work :-) )

You may encounter some error messages about missing encription sources. Don't be bothered by that. All the ordinary stuff will work without that.

 

Have a nice simulation

  Eilert

 

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