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srojas
Observer
Observer
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Registered: ‎05-20-2019

AXI 4 full slave burst length in Ultrascale MPSoC

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Hi,

I'm trying to start a AXI4-slave which receives data from the PS. This is in a Ultrascale MPSoC using Vivado 2020.1.

I have created the AXI slave with the IP Package Manager and managed to send data bursts from the PS.

  • I'm using the port M_AXI_HPM0_FPD with a width of 128 bit width.

I have noticed that the burst length does not exceed a value of 16.

Is this a restriction when transferring data from the PS to the PL? or I'm missing something? I thought, AXI4 it was supposed to support a burst length up to 256.

In the TRM (ug1085) of  the Ultrascale I found the following (Page 1062)

srojas_0-1611941832757.png

Is the PS than restricting the burst length?

King Regards,

Sebastian

 

 

 

 

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miker
Xilinx Employee
Xilinx Employee
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Registered: ‎11-30-2007

@srojas 

Yes.  The PS is AXI3 compliant where burst length is restricted to 16 (AMBA AXI and ACE Protocol Specification (IHI0022; p 48)).

You can reference the Zynq UltraScale+ Device Technical Reference Manual (UG1085; v2.2; p 1090) which further supports the PL-PS Interface reference you noted.

  • Chapter 35: PS-PL AXI Interfaces > FPD-PL Interfaces > PS-PL Interface Specifics

forums_zus_ps_pl.png

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miker
Xilinx Employee
Xilinx Employee
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Registered: ‎11-30-2007

@srojas 

Yes.  The PS is AXI3 compliant where burst length is restricted to 16 (AMBA AXI and ACE Protocol Specification (IHI0022; p 48)).

You can reference the Zynq UltraScale+ Device Technical Reference Manual (UG1085; v2.2; p 1090) which further supports the PL-PS Interface reference you noted.

  • Chapter 35: PS-PL AXI Interfaces > FPD-PL Interfaces > PS-PL Interface Specifics

forums_zus_ps_pl.png

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srojas
Observer
Observer
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Registered: ‎05-20-2019

@miker

Thank you for the reply.

You mentioned that the AXI FIFO Interface is the one limiting the burst to a length of 16.

srojas_6-1612185281134.png

srojas_7-1612185303664.png

srojas_0-1612184899818.png

If I wanted to increase the performance of the HP interface, there is no way to have a burst length of 256 for transmitting data between PS and the PL?

Is it possible to bypass it? 

Kind Regards

 

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miker
Xilinx Employee
Xilinx Employee
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Registered: ‎11-30-2007

@srojas 

I am not aware of an exception to the 16 beat burst for PS-PL transactions. What is your critical PS-PL path and what is the performance requirement you are trying to achieve?

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