cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
Highlighted
Visitor
Visitor
248 Views
Registered: ‎11-20-2018

AXI BRAM Controller: Second Write Burst

An IP Integrator configuration using an AXI DMA block configured for Direct Register Mode and an AXI BRAM controller will not perform a second Write Burst correctly unless an AXI reset is issued to the AXI DMA and AXI BRAM controller blocks.  What is preventing the second write burst from performing correctly without issuing a reset?

0 Kudos
1 Reply
Highlighted
Xilinx Employee
Xilinx Employee
198 Views
Registered: ‎11-05-2019

 

Hello @dmngz48 

Can you briefly explain your question? Are you saying you can't write correctly to address 0x40001000?

For AXI-DMA, AXI Stream data is input to the S_AXIS_S2MM port. It is output to the M_AXI_S2MM port by the Memory Map method.

Is there anything wrong with the AXI Stream data?

 

In addition, How did you set the Direct Register Mode of the AXI-DMA IP?  The AXI-DMA IP GUI does not have any such settings.

Thank you


Don't forget to reply, kudo, and accept as solution.

0 Kudos