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Observer
Observer
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Registered: ‎01-19-2018

AXI DMA Not Compatible with I2S Audio Receiver

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I am tryin to connect two built-in Xilinx IP modules using an AXI4 Stream interface, but they are incompatible. I am trying to use an I2S Audio Receiver, with it's master axis port connected to the S_AXIS_S2MM port on the AXI DMA block.

When I connect them and try to verify my Block Design, I get the following critical warning:

[xilinx.com:ip:axi_dma:7.1-9] /axi_dma_port
                   ########################################################### 
                   Interface connected to S_AXIS_S2MM does not have TLAST port
                   ###########################################################

Looking up more on the AXI4 Stream interface, the TLAST port is required for proper operation, so I am hesitant to move forward with my build without resolving.

These are two built-in Xilinx IP Cores, am I connecting the interfaces improperly? Perhaps is one of the cores older than the other and "not compliant" anymore? Sorry in advance for no screenshot, but the Block Design is too large to get any kind of resolution.

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Moderator
Moderator
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Registered: ‎01-09-2019

@tombsj 

So the AXI DMA IP requires the TLAST signal to properly operate (https://forums.xilinx.com/t5/Processor-System-Design/Axi-DMA-S2MM-Is-it-necessary-to-assert-TLAST/m-p/745101#M19137 - this explains a little bit of why and how the DMA operates).

PG308 shows the I2S IP and on page 25 it talks about the signals used.

I don't believe the I2S IP included this signal because it wouldn't know when the end of your audio stream was.  You will need to add this (through custom IP) in order to tell the AXI DMA when the end of a packet is at.  When TLAST is asserted would be based on the configuration of AXI DMA you set up in software.

Thanks,
Caleb
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Moderator
Moderator
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Registered: ‎01-09-2019

Hello @tombsj 

Could you send a picture of just the problem interface, and then maybe just the DMA and I2S IPs next to each other?

For the AXI DMA IP, TLAST is required to get a proper data stream.  Do you see the TLAST pin on the AXI Streaming port from your I2S IP?

Thanks,
Caleb
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Observer
Observer
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Registered: ‎01-19-2018

Hi @calebd 

Please see attached screenshot of the DMA and I2S IP cores next to eachother, please notice that on the I2S receiver there is no TLAST signal as a part of the m_axis_aud interface.

Thank you,

Josh

Screenshot from 2019-11-07 11-49-41.png
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Moderator
Moderator
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Registered: ‎01-09-2019

@tombsj 

So the AXI DMA IP requires the TLAST signal to properly operate (https://forums.xilinx.com/t5/Processor-System-Design/Axi-DMA-S2MM-Is-it-necessary-to-assert-TLAST/m-p/745101#M19137 - this explains a little bit of why and how the DMA operates).

PG308 shows the I2S IP and on page 25 it talks about the signals used.

I don't believe the I2S IP included this signal because it wouldn't know when the end of your audio stream was.  You will need to add this (through custom IP) in order to tell the AXI DMA when the end of a packet is at.  When TLAST is asserted would be based on the configuration of AXI DMA you set up in software.

Thanks,
Caleb
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