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Explorer
Explorer
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Registered: ‎04-18-2017

AXI DMA Receive by chunks

Hello,

I am using an AXI DMA to send/receive PS<->PL. So far I know how many bytes will be in total. However, in the stream of data that I receive from PL includes the first 4 bytes the total number of bytes in the complete message. The hardware I know works with TLAST but on the software side I am using the following code where I need to specify a number of bytes to receive:

// Taken from Xilinx's example
#define SIZE_ARR 300000 // MAX possible amount of bytes to receive
#define MEM_BASE_ADDR 0x21000000 // Give some offset to have a large buffer with the rest
#define TX_BUFFER_BASE (MEM_BASE_ADDR + 0x00100000)
#define RX_BUFFER_BASE (MEM_BASE_ADDR + 0x00500000) unsigned char *m_dma_buffer_RX = (int*) RX_BUFFER_BASE; ... // Flush cache Xil_DCacheFlushRange((u32)m_dma_buffer_RX, SIZE_ARR*sizeof(unsigned char)); // Set DMA to receive data from PL XAxiDma_SimpleTransfer(&axiDMA,(u32)m_dma_buffer_RX,SIZE_ARR*sizeof(unsigned char),XAXIDMA_DEVICE_TO_DMA); // Wait until data is received while(XAxiDma_Busy(&axiDMA,XAXIDMA_DEVICE_TO_DMA)) vTaskDelay(xDelay); // Read how many bytes have been received uint32_t len = getS2MMLenght(); // Invalidate memory to avoid loosing data Xil_DCacheInvalidateRange((u32)m_dma_buffer_RX,len*sizeof(unsigned char));

The issue here is that I have to know before hand the size for SIZE_ARR. So, what I would like to do is only read 4 bytes and once I know the amount of total bytes, allocate the exact memory space and then read them.

I duplicated the code by doing one read with 4 bytes and the second one with the known length but as TLAST never comes the complete transfer from PL does not happen and I get stack in the loop. Is there a way to circumvent this? Of course, removing TLAST would not work from the PL side. To be clear, I would like to avoid knowing before hand SIZE_ARR.

Thank you.

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Scholar
Scholar
288 Views
Registered: ‎05-21-2015

@aripod,

You could use a DMA that doesn't require TLAST, instead allowing you to specify and use the length once known.  Incidentally, it doesn't have the bugs that Xilinx's DMA has either ... Just a thought.

Dan

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Scholar
Scholar
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Registered: ‎03-28-2016

@aripod 

Most likely the best option is what you are already doing.  Program the DMA to receive a Max size buffer.  Let the TLast end the receive early.  Use the size info in the data to process the proper amount of data.

Doing a 4 byte transfer, reprogramming the DMA and then receiving the rest of the data is going to be difficult, as the DMA is not going to like it if data arrives before it has been properly configured for the second transfer.

Ted Booth | Tech. Lead FPGA Design Engineer | DesignLinx Solutions
https://www.designlinxhs.com
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Explorer
Explorer
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Registered: ‎04-18-2017

@dgisselqI have seen that, but what about the drivers for the SW?

 

@tedbooth  Yes, but by using the max buffer size removes the concept of tlast (avoiding to know max number of bytes to transfer....). So, HW and SW are a bit "contradictory"

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