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Adventurer
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Registered: ‎12-26-2016

AXI DMA multiple transactions - possible?

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Hi there,

 

I'm currently working on my master thesis and would like to implement a convolution core within frequency domain. The FFT and IFFT Cores are working fine with my current board design and the convolution seems to work correctly in the testbench. The whole design is synthesized and flashed into a Zynq020 from MYIR (Here's the product).

 

To increase the possible filter length and keeping latencies low I wanted to implement a Frequency-Domain Delay Line FDL Basic . Because I have no knowledge about CDMA or DMA SG modes and my time is running out I implemented a single DMA R/W Core for loading the filters and storing the convoluted data. All filter data and convoluted spectra will not fit into the BRAM cells.

 

This is my board current design. I do the math in the fft block, the DMA is in normal operation mode (see below)

Board Design FFT.jpg

ContentDMA.jpg

 

To do the filtering correctly I have to store the data from the Frequency-Domain Delay-Line into my DDR and load them later on. That has to be done for multiple (audio) channels so I have to do some memory management.

 

The memory management is currently done within the PS by doing some memcpy commands for 128 elements of int32 values. I guess the time to move my data in the PS is crucial. Currently I transfer one whole set of data between the DDR and the FFT Block, by now thats 6144 Bytes.

 

To minimize PS load I would like to try an alternate approach:

 

void myDMA_function(void) {
Xil_Out32( XPAR_AXI_DMA_1_BASEADDR + MM2S_SourceAddress, (unsigned int)fdl_current_address ); Xil_Out32( XPAR_AXI_DMA_1_BASEADDR + MM2S_Length, FDL_DMA_LENGTH ); // increase the address value to the next correct value //fdl_current_address = ...
// some processing but nothing long Xil_Out32( XPAR_AXI_DMA_1_BASEADDR + MM2S_SourceAddress, (unsigned int)fdl_current_address ); // is that possible? What happens if I write the MM2S_Length register again before transactions are done? Xil_Out32( XPAR_AXI_DMA_1_BASEADDR + MM2S_Length, FDL_DMA_LENGTH );
}

I could not find any hints on stopping me in the IP Documentation PG021 v7.1.

 

Do I need to switch to DMA-SG mode? Right now I have no clue on how that works. Do you have some nice examples :) ?

If you need more information don't hesistate to ask me :)

 

Thanks a lot!

 

Greetings

Thomas

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Adventurer
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Registered: ‎12-26-2016

Re: AXI DMA multiple transactions - possible?

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Right now I'm dealing with the DMA in Scatter Gather mode. It's easier for me to write a descriptor list and let the DMA do his job.

 

Nevertheless I found no clue about multiple transactions on the normal mode. I guess this will result in unresolved behaviour.

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Explorer
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Registered: ‎04-19-2018

Re: AXI DMA multiple transactions - possible?

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Hi, tmaintz.

I have the same board and worked on similar things (DMA, FFT). Struggled to make it work but succeeded at the end.

My answer to your concrete question:

You don't need to use SG, that is when you want to copy different chunks into a joint area or the other way round.

There are some basic example codes for DMA in the vivado installation (don't have now the path on the top of my head), I'd suggest you first try the polling version, then eventually move to the interrupted.

Do you process input data in 128 sample chunks? No straddle? Is the FFT integer?

Usually the DMA transfer time is very short compared to what the FFT takes. Why is it crucial?

Does that RTL FFT block do all the FFT - product - IFFT stuff?

 

 

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Adventurer
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Registered: ‎12-26-2016

Re: AXI DMA multiple transactions - possible?

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Hi @satguy,

thanks for the sharing!

 

I'd suggest you first try the polling version, then eventually move to the interrupted.

I did the interrupted version in my previous design. Via console I've seen my debug messages form the lines. I guess there is everything ok with that. So data is moving somehow and I'm pretty sure that data is correct.

 

Do you process input data in 128 sample chunks? No straddle? Is the FFT integer?

For the FFT I transform two real value signals (one declared as real part, other one as imaginary part) and seperate them in frequency domain. That works fine in the testbench. Even my design performed well in the Simulation. "Only" thing I've change was inserting the PS in the block diagram and synthesize the design (no timing errors reported).

 

Usually the DMA transfer time is very short compared to what the FFT takes. Why is it crucial?

I agree, the DMA transfer is very short. This DMA process isn't crucial but the data movement on the PS side is. My data needs to be restructured before I can move on with the processing.

 

Does that RTL FFT block do all the FFT - product - IFFT stuff?

The RTL Block does only the filtering in frequency domain. For the I/FFT I use the Xilinx FFT

 

@satguy: Did you used the interrupt DMA version in the end? Have you just used the DMA w/o PS shifting transferred data on the memory?

 

Greetings, Thomas

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Explorer
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Registered: ‎04-19-2018

Re: AXI DMA multiple transactions - possible?

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This DMA process isn't crucial but the data movement on the PS side is. My data needs to be restructured before I can move on with the processing.
You could benefit with an HLS block doing that process more efficiently. If you feel you have no time, you might try pipelining: after you capture the frame N, while frame N+1 is being fetched into memory, FFT (of frame N) is done, and when frame N+2 is being fetched, you do all that processing of frame N (plus FFT of frame N+1). That increases the memory needs, but I assume frames of 128 aren't going to be a problem.

 

Yes, my DMA works with ints, my problem was not interrupt related so once I fixed it in polling mode there was no problem. 


I don't get what you mean with "DMA w/o PS shifting transferred data on the memory". with DMA, you tell it to send N bytes starting at that address and it happens. As well as the reverse: you tell it to receive N bytes and write them at some address and wait for it. This is DMA between memory mapped and stream. 

 

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Adventurer
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Registered: ‎12-26-2016

Re: AXI DMA multiple transactions - possible?

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I want to implement a frequency domain delay line: See here for a picture

 

The gray colored part contains the just transformed data and will be processed by different filters. Each time the FFT starts to calculate the spectra I start a DMA R operation and transfer the filters and prior calculated spectra to my RTL code.  To store the calculated spectra I use the DMA W in one AXIS transaction. The system needs to be causal, so each filterpart has to be delayed by one FFT cycle.

 

When I do that like this I'll have data in the DDR which needs to be restructured. To get my data in the correct order I use the PS with a memcpy/memmove operation each time the DMA R/W is done and the data is present in the DDR. The benefit is that the DMA transfers always a preordered set of data and the management of that will be done by the PS which runs at higher frequencies. And thats the point where I struggle. I don't know whether the PS is fast enough for my restructure operation.

 

If there is still something unclear don't hesistate to ask :)

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Adventurer
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Registered: ‎12-26-2016

Re: AXI DMA multiple transactions - possible?

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Right now I'm dealing with the DMA in Scatter Gather mode. It's easier for me to write a descriptor list and let the DMA do his job.

 

Nevertheless I found no clue about multiple transactions on the normal mode. I guess this will result in unresolved behaviour.

View solution in original post

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Moderator
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Registered: ‎06-29-2011

Re: AXI DMA multiple transactions - possible?

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Hi @tmaintz

 

I am not a AXI DMA expert or with the FFT and IFFT cores but I see that you are struggling with understanding how to work with the AXI DMA. We have some examples in AR:57550 that detail AXI DMA in polled mode, it then expands on this and used interrupt mode and then it expands on this again to add AXI DMA in Scatter Gather mode, finally there is an example of a Zynq-based FFT co-processor using the AXI DMA which I believe will be helpful for you.

 

The recommendation is to start with polling mode and work to the final solution to get a good understanding of the AXI DMA. The examples can be found at the following link.

 

AR:57550 - Example Designs - Designing with the AXI DMA core

https://www.xilinx.com/support/answers/57550.html

 

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Kind regards,
Gareth
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