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artg
Observer
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Registered: ‎05-20-2014

AXI DMA tready problem

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Hey,

 

I am trying to implement a way to transfer data from a custom peripheral to the ddr ram of the ARM. My custom IP has an axi-stream interface which is connected with a axi-stream FIFO. I know that the data is written in the FIFO. I read back the wr_data_count and this value will increase until its maximum is reached.

 

The Master interface of the Fifo is connected to my axi-dma. During testbenching I found out that the only way to get wr_data_count to reach its maximum is when the master_tready signal is kept low. Therefore it seems that this is the case in my setup. 

 

 

I used the xaxidma_simple_poll to initialize my DMA and I use a XAxiDma_SimpleTransfer function to start the DMA before I start the transfer of data from the custom IP

 

 Can someone tell me what I do wrong ?

 

Thanks,

FifoDmaConnection.png
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artg
Observer
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Registered: ‎05-20-2014

 

Hello bwiec,

 

Thanks for your reply,

 

Today I solved my problem. I have removed the fifo and connected my pheripheral directly to the dma controller. I also had to implement the tlast flag, because the DMA  controller kept saying it was busy with a transfer although all my data was already in the memory. After implementing the tlast on the last byte of every frame my system works fine.

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bwiec
Xilinx Employee
Xilinx Employee
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Registered: ‎08-02-2011
Hello,

A few questions
- Does tvalid ever go high from the FIFO?
- Can you dump the DMA registers and post them?
- Check on clocks, resets, and clock enables
www.xilinx.com
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artg
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Registered: ‎05-20-2014

 

Hello bwiec,

 

Thanks for your reply,

 

Today I solved my problem. I have removed the fifo and connected my pheripheral directly to the dma controller. I also had to implement the tlast flag, because the DMA  controller kept saying it was busy with a transfer although all my data was already in the memory. After implementing the tlast on the last byte of every frame my system works fine.

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astei87
Adventurer
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4,547 Views
Registered: ‎09-03-2015

Hello Guys, 

i have a similar problem. I have an IP which streams data over a FIFO and a DMA to the RAM. (same picture like obove)

After a time, the frame receiption stops. The tready from the DMA to the FIFO goes to 0. 

It is a big design, where i have the 10G Ethernet IP from Xilinx also in. I cannot say when excatly the tready goes down, because

its alsways different. Sometimes after 1 second, sometimes after 30 seconds and so on...

My assumtion is, that someone else blocks the RAM. But how can i find it out?

Is it possible to see the status from the DMA or any loggings? Thanks

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bwiec
Xilinx Employee
Xilinx Employee
4,534 Views
Registered: ‎08-02-2011

Hello,

 

My assumtion is, that someone else blocks the RAM. But how can i find it out?

Are you saying tready deasserts indefinitely? If yes, I'd be surprised if this is the issue. If it's a memory bandwidth issue, you'd most likely see tready toggling up and down periodically, not indefinitely deassert.

 

Is it possible to see the status from the DMA or any loggings? Thanks

Yes, this is what I'd do next. Dump the status registers of the DMA and check for errors.

 

Some questions:

- Are you using the linux driver or is this baremetal?

- Are you using scatter gather?

- How big are your incoming packets? Are they variable? How does your software handle this?

 

www.xilinx.com
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astei87
Adventurer
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Registered: ‎09-03-2015

hi bwiec, thanks for your help

 

Yes tready deasserts indefinitely. 

I cannot see any errors from the DMA.

I use the linux driver. I have no scatter gather. The packages have width of 48 Bit.

After 3.5 MB comes the tlast. 

 

design.JPG

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astei87
Adventurer
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4,509 Views
Registered: ‎09-03-2015

i think i found out the problem. I don't use the tready wire from the axi_dwidth_converter to the IP. Because i have to send always. But it seems, if i debug this wire, it works. I think the axi_dwidth_converter needs a termination of tready. Otherwise vivado will clean out important logic in the axi_dwidth_converter IP i guess.

pear
Visitor
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Registered: ‎05-23-2018
Hi artg,

Can you tell me where to edit the tlast flag? In the SDK code or ip vhdl? I am quite confused. Thank you.
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