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Alirezam
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Registered: ‎11-20-2020

AXI-Full Slave configuration

Hi

i am new to AXI. after reading the specification of AXI Protocol, i created the axi-lite ip and modified it to sum 2 numbers. it works fine. 

now i make axi-full slave ip and want to write some variables in some locations. the problem is that i dont know how to set the burst or awlen?! where should i write to config these parameters?!

in axi-lite there were some registers and when i wrote to base address, data would written to slv_reg0 . but in axi-full i faced by too many signals and i dont know how to set them. 

i tried some ways like using Xil_Out32(); commands but my application didnt work!

i searched about this issue but nothing found! maybe i used wrong keyword!

where i can find useful user manual!?

thanks

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dpaul24
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Registered: ‎08-07-2014

@Alirezam,

now i make axi-full slave ip and want to write some variables in some locations.

That can be done without burst access. Single W accesses to increasing memory locations. But it seems you want to make your slave full AXI4 compatible, right?

the problem is that i dont know how to set the burst or awlen?! where should i write to config these parameters?!

The slave should be supporting it, it does not need to create it. The burst or AWLEN is set by the master doing a R/W access to the slave. So when burst requests are placed by a master the slave should latch those values until the burst access is completely over.

where i can find useful user manual!?

AMBA AXI4 spec nothing else. Download - ARM IHI 0022E (ID022613). Re-reading it multiple times is quite normal, a full AXI4 protocol is overwhelming.

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Alirezam
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Registered: ‎11-20-2020

Thanks for your answer

The slave should be supporting it, it does not need to create it. The burst or AWLEN is set by the master doing a R/W access to the slave. So when burst requests are placed by a master the slave should latch those values until the burst access is completely over.

i knew that slave should support it. when using vivado "create and package IP", the code generated by the vivado supports burst, after re-packaging slave IP, i use zynq processing system as a master, now master should determine the value of burst or awlen or ... 

i want to know how master understand to use burst or not?! when using xil_out32, we should determine specific address and value (does cpu config burst on "00" itself?!) but when i want to write in burst mode, what should i type in sdk to show i want to use burst?! (is there a command that when used, sdk know it's burst transaction!?)

thanks for your time

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dpaul24
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Registered: ‎08-07-2014

i use zynq processing system as a master, now master should determine the value of burst or awlen or ...

Yes.

i want to know how master understand to use burst or not?

By driving the signals awlen, awsize and awburst to their proper values.

but when i want to write in burst mode, what should i type in sdk to show i want to use burst?!

How to do that in SDK/Software that I do not know. I have always done it in hardware (RTL).

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dgisselq
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Registered: ‎05-21-2015

@Alirezam ,

Welcome to the wonderful world of AXI.  The first thing you need to know is that Xilinx's training materials are broken.  If you use "Create and Package new IP", Vivado will generate a broken design for you.  It may work for some time, long enough to convince you that it works, but it is not specification compliant.  Some environments will trigger the bugs.  When they do, anything connected to that AXI bus (typically the entire design) will then hang and hang unrecoverably hard.  Well, perhaps not completely "unrecoverably": A system reset should still cure the problem.

The second thing you should know about Xilinx's AXI demonstration slaves is that they get horrendously poor throughput.

I certainly wouldn't recommend that you start with Xilinx's examples.  You can find better examples of actually working AXI slaves and masters on ZipCPU.com.  You'll also find a lot of instructional material there.

As to your questions, I recently discussed how to get the ARM to generate burst requests of your programming logic (PL), as well as the paucity of training material in general. Basically, if you tell the ARM that the FPGA logic area containing your slave.contains cachable memory, then you can get the ARM to issue a burst request.  This is typically counter productive, since your general purpose in building programming logic to be interacted with is so that you can change things.  Also, other than cache accesses, CPU's don't generate burst requests since CPU's only ever handle one instruction at a time.

A better way of getting burst requests is to use a data mover of some type.  These direct memory access (DMA) controllers act like basic hardware memory copies.  They can move massive amounts of data at high speed--or at least that's what they are designed to do.  (See the link above for some issues associated with them.)

As for AxBURST, well, that's another thing Xilinx's example AXI full slave messed up.  Indeed, their address handling completely breaks down for bus sizes of 8-bits of anything greater than 64 bits.  That's one bug.  If I recall correctly, their burst handling logic only implements the logic necessary for AxSIZE values of 3'b010.  Check out the "Understanding AXI Addressing" article on ZipCPU.com for a description of how to handle that properly--for all values of AxSIZE, AxLEN, and AxBURST, as well as example logic for doing it right.

Dan

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