03-29-2020 05:35 PM
I'm new to AXI. I'm trying to do the following
1. Create the most simplest design possible in AXI -- Hello World -- equivalent.
2. Simulate the design in Vivado -- observe AXI signals
side-note: I'm tired of reading the same info again and again in blogs. How there are different channels and how there are transactions (and associated control signals/channel). I want a simple design that I can create and simulate so that I can get a hang of what is happening.
1. What would be the most simplest design ?
2. Right now I have this simple design: the AXI-master of AXI_BRAM_CONTROLLER connected to the AXI-slave of a BRAM. In order for me to write to the BRAM, I need to drive the AXI-slave of the AXI_BRAM_CONTROLLER. Do I need to write an IP to do this (read AXI manual, understand and then write an IP that sends the write instruction) ?
03-29-2020 07:05 PM
Xilinx has put together a lot of training materials surrounding their IP packager, recommending that you use the IP packager to create a simple and basic AXI core for you. The basic idea isn't all that bad: you pick the Vivado menu option for "Create and Package New IP", and then Vivado generates an AXI component for you to modify--the only problem is that the AXI slave cores the IP packager generates for you aren't AXI compliant. If you use them, you will risk your design hanging up on you.at some later time. (I'm sure Xilinx simulated these designs at some point. The training material even discusses using their AXI VIP to try to find bugs in their cores. It's just that these methods weren't sufficient to find all the bugs in these demonstration designs.)
To make matters worse, there are a lot of AXI designs on the web that are broken. One slave example design I remember coming across had a giant state machine for processing the incoming AXI transaction. Only ... the slave never checked nor expected read and write requests on the same clock cycle--a very real possibility. If such a transaction request ever came in, for a read and write request, the design would either drop one of the two requests or hang.
One of Xilinx's (broken) designs tries to limit the design to reads or writes but never both. (They weren't successful) AXI is intended to be a full duplex bus that handles reads and writes at the same time. (Otherwise Wishbone would be a whole lot cheaper and easier to work with.)
As an alternative to Xilinx's broken example designs, let me offer some other cores you can use to start from. You can find them discussed on my ZipCPU blog and posted in my ZipCPU/wb2axip github repository. I've recently blogged about building an AXI-lite slave core the easy way . There's an older article on the same blog about building a full AXI slave. Another one of the more recent posts discusses building an AXI master. Each post contains discussions of example code and links to the full example. There's also a post, dating back to December of 2018, discussing how you can go about verifying an AXI-lite slave (and finding the bugs in Xilinx's IP packager slave that weren't found in their simulations.) All of the examples, linked from each of the posts, link to the same ZiPCPU/wb2axip github repository. (I'd offer links to all of these, but if I did so my post would get marked as spam--and that just wouldn't help you much.) If you do check out the ZipCPU/wb2axip repository, feel free to check out the doc/gfx directory for a series of PNG files documenting traces showing how the various cores works (at its best and fastest). That plus the blog might help you understand more of how AXI works.
Unfortunately, Xilinx didn't pick an easy bus standard to interface with. Indeed, there's a recent Reddit discussion on the FPGA reddit asking whether or not AXI is too complicated in the first place. Then, rather than make things any better or simpler, their new AXI5 standard just makes things even more complicated.
It's doable, but be aware of what training materials you start from.