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Observer
Observer
330 Views
Registered: ‎09-27-2014

AXI IIC Pulse Train after NACK

i2c_write_code.png

 

i2c_pulse_train_error.png

 

 

I'm using AXI IIC module with Microblaze in Vivado 2018.3.

I have a problem in resetting target slave device which have 0x70 of slave address.

When I write some data to I2c Slave Target to reset that device.I got SCL pulse train until I reset I2c bus. this causing I2c Bus Busy and errors.

STOP conditions not coming even that I scheduled to write STOP command to TXFIFO (0x108) with 0x280 (0x200 is STOP Command in AXI IIC module)

Please tell me if there anything that I have to reset this state.

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Xilinx Employee
Xilinx Employee
299 Views
Registered: ‎09-01-2014

Please make sure you don’t disable the IIC when trying to flush the FIFO.

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