03-11-2021 05:29 PM
Set up an ILA on the output of the AXI interconnect to an AXI BRAM controller. Noticed this strange behavior where, as soon after the fpga is configured, the ARADDR and AWADDR are toggling between x88 and 0x00 indefinitely but no AxVALIDs are occurring. This address toggling continues until the first AWVALID and ARVALID occurs. So, AWADDR keeps toggling until the firsts AWVALID occurs and vice versa. After that addressing is correct based on whatever write and read operations occur.
On the other side of the interconnect there are two MicroBlazes running hello world, and and external AXI Master, and a JTAG-AXI master. I'm certain that the JTAG-AXI or the external AXI Master isn't changing the addresses.
Version of Vivado 2020.1, in Linux.
03-30-2021 03:59 AM
Weird simulation behavior can occur if the axi reset isn't at least 16 clocks.
03-30-2021 04:06 AM
You mentioned simulation behavior, does that imply behavior in the hardware as well? I would assume that the reset out of the Proc System Reset has the proper reset length that it provides to the AXI Interconnect, etc. The screen captures that I provided are ILA captures.
04-30-2021 09:06 AM - edited 04-30-2021 09:07 AM
Yes, this implies for the hardware as well.
Xilinx IP with AXI interfaces generally require synchronous resets that are asserted for a minimum of 16 AXI clocks. And yes, the Processor System Reset IP helps to insure all IPs receive a reset that meets this requirement.