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Registered: ‎03-27-2020

AXI Interconnect awready/arready not going high on one SI

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Hi all,

I have a 2 to 1 AXI interconnect with two masters sharing access to one slave memory controller interface. One of the masters connected to S00 is at 125MHz, and S01 is at 400MHz. The interconnect clock and reset_n is the same as S01s clock and reset_n, and so is M00 (the axi interface to the MIG). S00 has its own synchronous reset_n. 

The problem is on S01, the awready/arready signals never go high. They are going high on S00. I switched the slave interface ports, redid the block design and all, and I'm not sure what the problem could be. Any help would be appreciated. Thank you!

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Registered: ‎05-21-2015

Re: AXI Interconnect awready/arready not going high on one SI

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@jsmith404040,

Ok, back up ... you aren't setting WVALID ever?  This is a violation of the protocol.  You aren't allowed to wait for AWREADY before setting WVALID.  As the answer record points out, many of Xilinx's AXI slaves wait for AWVALID & WVALID before raising AWREADY.  Even in my own implementations, some of my slaves will hold AWREADY low until both AWVALID & WVALID.  (and also until !BVALID || BREADY ...)

That would be a bug in your design.

Dan

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Re: AXI Interconnect awready/arready not going high on one SI

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@jsmith404040,

Let me ask about your AXI reset first, since you said that each of the master cores was reset separately from the interconnect.  Have you guaranteed that all cores are reset at the same time, and that the masters are released from reset either at the same time as the interconnect or just after the interconnect?

Another common AXI confusion is that all VALID signals are supposed to be low on the clock following any reset assertion, not just during the reset assertion.  It's at least something to check for.

Dan

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Re: AXI Interconnect awready/arready not going high on one SI

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@dgisselq ,

Master core 0, the interconnect, and the slave core run on the same clock (400Mhz), and master core 1 runs on a different clock (125MHz). How would I go about verifying that the resets happen at the same time? I would think to use the xilinx ILA cores and trigger them at startup, but since they're on different clocks (therefore different ILAs) how would I be able to tell the resets overlapped?

In the meantime, I'm going to connect master core 0 twice to the interconnect and run the entire thing on one clock to see if that fixes any problems.

Thanks,

Jaden

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Re: AXI Interconnect awready/arready not going high on one SI

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@jsmith404040,

Well, okay.  400MHz is kind of fast.  It is possible that things won't meet timing.  Have you double checked that your design meets timing?

Beyond that, I'd have to see your core to see what's going on.  I've seen a lot of bugs that would do this sort of thing, but its hard to be specific about which is causing it.  Perhaps the most common case is a transaction that was accepted that you weren't expecting.  Perhaps AWVALID && AWREADY but your state machine didn't advance.  Perhaps WVALID was true, but never WLAST.  As a result the interconnect is waiting for more information before it will raise the respective ready lines.  I can't really tell, though, since you haven't shared your master's design.

Dan

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Re: AXI Interconnect awready/arready not going high on one SI

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I'm sure the design meets timing. The state machine driven by the 400MHz clock works - I've tested it by a direct connection to the MIG AXI as the slave (without an interconnect). The issue happens when I try to add another master. WVALID and WLAST are never set - I'm not even getting to that point because:  my state machine waits for AWREADY before raising AWVALID.

Weird, though, from this link:

https://www.xilinx.com/support/answers/63381.html

It says that slaves wont raise ready until valid data and address is on the channel. What gives? In that case, the other master (125MHz) must be wrong, because the awready and arready are high on that channel. Furthermore, why did my original master to MIG 1:1 connection work? 

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Re: AXI Interconnect awready/arready not going high on one SI

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@jsmith404040,

Ok, back up ... you aren't setting WVALID ever?  This is a violation of the protocol.  You aren't allowed to wait for AWREADY before setting WVALID.  As the answer record points out, many of Xilinx's AXI slaves wait for AWVALID & WVALID before raising AWREADY.  Even in my own implementations, some of my slaves will hold AWREADY low until both AWVALID & WVALID.  (and also until !BVALID || BREADY ...)

That would be a bug in your design.

Dan

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Re: AXI Interconnect awready/arready not going high on one SI

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@dgisselq 

You were right, I set valid high and ready became high as well. Spent way too long debugging this. Thank you!

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