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Explorer
Explorer
5,054 Views
Registered: ‎05-11-2012

AXI Master Burst Transfer Errors

I have a custom IP that was first created in the Create/Import Peripheral Tool of XPS, but has been modified with some custom logic.  This custom IP acts as a Master on the AXI4 bus that has a 128-bit data width for our design.

 

I have been testing this IP through simulations lately and am seeing errors in the following case:

As a master on the AXI4 bus (128-bit data width), I attempt to write 16 bytes or 1 beat to a specified offset in BRAM. This write fails in all attempts and reports an error as sig_tlast_err_ovrrun from the Wr_Cntrl of the AXI_Master_Burst module of the custom IP.  If I change the attempted write to be 32 bytes at any offset, then I don't see any errors.  

 

Is there a way to transfer 16 bytes of data to a specified memory location using the AXI_Master_Burst LogiCore as a part of this custom IP, or must the transfer always be at least 32 bytes?

 

Where can I find information about what causes the sig_tlast_err_ovrrun and sig_tlast_err_undrrun errors to occur?

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6 Replies
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Explorer
Explorer
5,035 Views
Registered: ‎05-11-2012

Re: AXI Master Burst Transfer Errors

Does anyone have any information on this issue?

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Explorer
Explorer
5,022 Views
Registered: ‎05-11-2012

Re: AXI Master Burst Transfer Errors

Any help on the above issue would be appreciated!

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Visitor
Visitor
3,735 Views
Registered: ‎04-09-2014

Re: AXI Master Burst Transfer Errors

i have the same question.when i write 32B(128bit ) ,there is no error. but when i write 16B,error happen.why?

axi4 not support  random burst lengths?

 

 

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Explorer
Explorer
3,700 Views
Registered: ‎05-11-2012

Re: AXI Master Burst Transfer Errors

I never got an answer as to why I saw the error when I write 16B, but not when I write 32B.  I eneded up adding logic to my custom IP that prevents writing less than 32B, but makes sure it is a multiple of 16B for the transfer length.

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Teacher
Teacher
3,579 Views
Registered: ‎03-31-2012

Re: AXI Master Burst Transfer Errors

can you describe your configuration in more detail? It seems like you have a 16 byte (128 bit) master connected to an axi interconnect which has one bram slave, yes? Can you trace which device in the chain giving the error? Is it the bram controller or the interconnect?
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Explorer
Explorer
3,450 Views
Registered: ‎05-11-2012

Re: AXI Master Burst Transfer Errors

My design contains 3 custom IPs that all have 128 bit Master interfaces connected to 2 slaves that also have 128 bit interfaces.  I had no way to trace whether the Interconnect or the Slave was the root of the error, but the same error was seen for accessing both slaves (BRAM and DDR3).

 

As I said before, we placed custom checks in the custom IPs so that the minimum transfer length was 32 bytes as a work around for the issue since I could never get any help with the issue.

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