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kharalan
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Registered: ‎09-27-2018

AXI Multi-channel DMA interleaving granularity on stream side

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Hi,

Similar question was posted back in 2014 for the old AXI DMA IP core.

https://forums.xilinx.com/t5/BRAM-FIFO/AXI-DMA-multi-channel-interleaving-granularity-on-stream-side/m-p/509725#M2151

 

I have the same question for the new AXI multi-channel DMA. PG288 does not provide much information on TDEST.

Can I have packet size in the megabytes, but change TDEST on 16 or 32 bytes instead only at the begging of the packet in order to interleave packets from different streams?

 

Thanks!

 

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demarco
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Xilinx Employee
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Registered: ‎10-04-2016

Hi @kharalan,

I confirmed with the designers: interleaving is not supported on the S2MM path.

 

Regards,

 

Deanna

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demarco
Xilinx Employee
Xilinx Employee
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Registered: ‎10-04-2016

Hi @kharalan,

For an MM2S transfer, the TDEST is not configurable. It indicates which MCDMA channel sent the stream transfer.

 

For an S2MM transfer, TDEST indicates which MCDMA channel should process the incoming stream. I need to confirm the behavior of AXI MCDMA if a stream comes in with a new TDEST before the arrival of TLAST on the previous stream.

 

Regards,

 

Deanna

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kharalan
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Registered: ‎09-27-2018

Just to clarify - the question was about the S2MM transfer.

We have  couple of fast ADC and we want the DMA packet/transfer to be several Mbytes, but we can't buffer that much per channel in the FPAG to have the whole packet form one channel sent first and then send the second.

The alternative is to use 2 regular AXI DMA engines, but the multi-channel one have some other advantages.

Thanks!

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demarco
Xilinx Employee
Xilinx Employee
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Registered: ‎10-04-2016

Hi @kharalan,

I confirmed with the designers: interleaving is not supported on the S2MM path.

 

Regards,

 

Deanna

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