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ryandunn
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Registered: ‎04-28-2020

AXI Quad SPI Read Transaction

I am using the AXI Quad SPI IP in standard mode as a master to control several slave peripherals. I have been able to execute write transactions successfully. Now I am trying to execute read transactions to perform a readback of the slave peripheral registers. To do this, the timing diagram below from the slave peripheral indicates the following steps are required:

  1. Set the slave select line (CSB) low.
  2. Write an 8-bit value containing the R/W bit and the 7-bit slave address.
  3. Continue driving the clock (SCK) for 16 more cycles to clock out the register value.
  4. Set the slave select line (CSB) high.

image.png

I can't find anything in the documentation that describes how to do this. From simulation, I can see that reading from the data receive receiver (DRR) expects that the data is already available, and it does not enable the SPI clock to clock the data in.

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sarah77wicker
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Registered: ‎11-05-2018

hi did you get any update on this issue?

I am looking to do the same using the axi-spi ip from xilinx. As for you, transmission of data is working well but reading part is where my issue is. driver/ip read directly what is present on the line but i need it to wait for at least 10 rising edge of spi_clock before.

I thought of 2 solutions:

- inserting timing constraint on my input line in the pl design (using similar constraint as specified in this support page :https://www.xilinx.com/support/answers/59893.html)

- or modifing the driver becasue actually when i am transfering data, depending if i would like to read or write, i add a command control. So i need to read this one and in function of the value: it starts reading or writting.

I am currently working on the second option but it's prove to be quite some hassle i find. Any help or hint would be super

best regards,

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ryandunn
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Registered: ‎04-28-2020

No, I have not yet been able to figure out how to initiate read transactions using this IP.

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