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ba5eb@ndj
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Registered: ‎08-14-2017

AXI Quad SPI example IP Project does nothing

Hi,

 

I'm new to the AXI Quad SPI IP.  I have an FPGA that controls a Clock IC through SPI.  The FPGA gets commands from a processor.  I want to use the AXI traffic generator to initialize the Clock IC and then use my own state machine that generates AXI transactions to the Quad SPI.  The example IP Project for AXI Quad SPI does not simulate the address transactions that are in the .coe files when simulated.  How do I get the example IP project to work in Vivado 2016.4?

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ba5eb@ndj
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Registered: ‎08-14-2017

I run the Implementation and then the run post implementation timing simulation and the spi bus only raises the ss bit high and then io0 bit flips twice.

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