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Registered: ‎02-21-2015

AXI Slave interface for IP: Cost in clock cycles?

I created some nifty IP with HLS and was very excited to control it from the PS.

I specified an AXI Slave interface for reading and writing parameters to the function.


I am finding that each call to control the IP through the AXI slave interface consumes about 25 cycles of the PL clock.


Does this seem reasonable?


I am finding that the performance gains from realizing my design in PL is lost due to the interface.

My code resembles:

1. Set inputs: XHls_myip_Set_param1(&myhls, value);

2. Start the function: XHls_myip_Start(&myhls);

3. spin until interrupt arrives.

4. Read the function output: foobar = XHls_myip_Get_param2_o(&myhls);

5. Repeat.


Each call to XHls_myip function require about 25 clock cycles and it is starting to add up.


Can you suggest a faster way to get data to/from the IP? Is this the point where I learn about AXI Streams?




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Registered: ‎03-31-2012

the latency between ps & pl is on the order of 100 PS cycles at 660 MHz ie ~150ns. Depending on the size of the data needed to be transferred, the communication overhead will reduce your processing speed advantage. Using the processor to send individual words of data to the PL is a very slow method and it should be used only for very basic communication signals to a slave. The better partition is to make a control slave and a data transfer master in the PL. The slave receives the commands and addresses and the master in the PL reads all the source data through a high speed axi port (HPx or ACP), lets the processing engine do its job and write the data back similarly. 

- Please mark the Answer as "Accept as solution" if information provided is helpful.
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