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bill.whitehead
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Registered: ‎09-02-2013

AXI SmartConnect - Responding to Read before accessing other IP block

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I am using Vivado 2018.2.  I have two AXI Slave IP blocks that I have connected through an AXI SmartConnect 1.0 block to the ZYNQ PS7 M_AXI_GP1 port.  One is just a bunch of Registers for control and status of my other IP blocks.  The other acts an interface to BRAM located in my design to read and write.  I can write to both of my IP just fine.  When I try to read from either IP, I get a problem.  I am simulating using the ZYNQ VIP and using the VIP API.  Here is a part of the log from the simulation.  The writes work fine.  The VIP appears to finish the first Read and hangs on the second read.

 

 

[2985] : M_AXI_GP1 : *ZYNQ_VIP_INFO : Starting Address(0xb9000700) -> AXI Write -> 4 bytes
[3346] : M_AXI_GP1 : *ZYNQ_VIP_INFO : Done AXI Write for Starting Address(0xb9000700) with Response 'OKAY'
Writing memory: Response is 0
i is           0, Main area write b9000700 = deadc0de
Writing memory: b9000704 = deadc0df
[4095] : M_AXI_GP1 : *ZYNQ_VIP_INFO : Starting Address(0xb9000704) -> AXI Write -> 4 bytes
[4480] : M_AXI_GP1 : *ZYNQ_VIP_INFO : Done AXI Write for Starting Address(0xb9000704) with Response 'OKAY'
Writing memory: Response is 0
i is           1, Main area write b9000704 = deadc0df
... (writes a total of 8 32-bit registers) ....

[10605] : M_AXI_GP1 : *ZYNQ_VIP_INFO : Starting Address(0xb900071c) -> AXI Write -> 4 bytes [11013] : M_AXI_GP1 : *ZYNQ_VIP_INFO : Done AXI Write for Starting Address(0xb900071c) with Response 'OKAY' Writing memory: Response is 0 i is 7, Main area write b900071c = deadc0e5 [13245] : M_AXI_GP1 : *ZYNQ_VIP_INFO : Starting Address(0xb9000700) -> AXI Read -> 4 bytes [13347] : M_AXI_GP1 : *ZYNQ_VIP_INFO : Done AXI Read for Starting Address(0xb9000700) with Response 'OKAY' Reading memory: b9000700 = 00000000, 00000000, 0 i is 0, Main area reads b9000700 = 00000000 [14085] : M_AXI_GP1 : *ZYNQ_VIP_INFO : Starting Address(0xb9000704) -> AXI Read -> 4 bytes

 

As can be seen in the screen capture below, the AXI SmartConnect responds to the read request before it has issued a request to my IP block.  That doesn't seem right.  If this is true, then I have a time machine!  Why is the AXI SmartConnect not waiting for my IP block to respond before responding to the PS7 master?

 

 

SmartConnectError.png

 

The other IP behaves similar, but there the RREADY signal never asserts from the AXI SmartConnect to my IP block.

 

Something is going on with the SmartConnect and I don't know what to change to modify this.  I tried a quick experiment with AXI Interconnect but had an error with the AXI interface between the PS7 and the AXI Interconnect in simulation.  So I pulled that out and came back to the SmartConnect block.

 

I have build this and tried it on my ZYNQ board.  It does hang the processor when I try to read from my block.

 

Bill

 

EDIT: I just created a simple project with PS7, Reset block, SmartConnect, and my two IP blocks.  I only enabled the M_AXI_GP1 port on the PS7.  It is working fine in that simulation.  I am creating my block diagram from a TCL script.  Not sure what is going on.  Maybe something in the generation for synthesis and/or simulation is getting confused.

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bill.whitehead
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Registered: ‎09-02-2013

Hi @florentw,

 

My FAE was able to initiate a Xilinx SR for this issue.  I was able to remove our IP from the module being referenced.  The stripped down version also exhibited the AXI SmartConnect issue.  This has been given to the FAE and Xilinx to better troubleshoot.  I will go ahead and mark this forum posting as closed.

 

I am using Vivado 2018.2.  The reset is asserted at the start of the simulation with the minimum number of clock cycles satisfied while the reset is active (active low) which is 16 in the PG247 page 33. 

 

Bill

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florentw
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Registered: ‎11-09-2015

Hi @bill.whitehead,

 

What vivado version are you using? Could you share a test case?

Are you resetting the interconnect at the beginning of the simulation?


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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bill.whitehead
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Registered: ‎09-02-2013

Hi @florentw,

 

My FAE was able to initiate a Xilinx SR for this issue.  I was able to remove our IP from the module being referenced.  The stripped down version also exhibited the AXI SmartConnect issue.  This has been given to the FAE and Xilinx to better troubleshoot.  I will go ahead and mark this forum posting as closed.

 

I am using Vivado 2018.2.  The reset is asserted at the start of the simulation with the minimum number of clock cycles satisfied while the reset is active (active low) which is 16 in the PG247 page 33. 

 

Bill

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jduca
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Registered: ‎04-05-2011

What is the solution? I have the same issue and would like the solution posted please! Thanks!

John

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