My block design have a lot of peripherals which accessed via cascaded AXI. Top level is AXI Interconnect and others are SmartConnect (it is related to issue that cascaded SmartConnect implement full AXI4 with huge resource usage). SmartConnect core can be configured up to 16 master interfaces. But peripherals connected to ports M08-M15 are not accessible. They are shown in the category "Unconnected" in the address map. Moreover, the structure of SmartConnect core which shown in the Advanced properties has 8 master ports (M00-M07) only.
Design validation produces following error:
ERROR: [BD 41-703] Slave segment </JESD/axis_mux_0/S_AXI/reg0> is mapped into master segment </ps_ddr/zynq_ultra_ps_e_0/Data/SEG_axis_mux_0_reg0>, but there is no path between them. Please delete the master segment or check your design to ensure a valid path can be created.
The practically difficult part about arbitrarily increasing the number of masters an interconnect can handle is that you'll necessarily slow it down. While Xilinx 7-series parts support MUX8's in raw hardware, it takes a bit more hardware to generate higher order muxes. Expect higher resource usage therefore and possibly even a slower bus speed. Whether or not your speed is limited by the interconnect or not is going to be design dependent.