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Registered: ‎04-29-2014

AXI Stream FIFO RDFO Register always zero

I have been trying to implement a fifo to offload data from the fabric into the MicroBlaze. I am using the VC707 bev board, and Vivado 2014.2. I have a counter that is generating data and driving the AXI stream fifo. A general block diagram of the system can be seen in the attached JPG. I started with the Xilinx Interrupt FIFO Example c code. I modifed the example code to only read from the FIFO because the data is coming from my counter on the FPGA. I added some printf statements and if I run the code I get the following output:

 

--- Entering main() ---

Receiving Data...

Errors: 0

ReceiveLength = 3

RDFO Register = 0x0

Receiving Data...

Errors: 0

ReceiveLength = 3

RDFO Register = 0x0

 

The c code is attached.

 

The FIFO understands that it has three words of data in the fifo, but the RDFO is always zero. I am setting the tlast flag (as seen in the attached debug figure) on the thrid piece of data.

 

I changed the size of the data in the fifo_intr.c file to show three packets:

 

#define WORD_SIZE 4            /* Size of words in bytes */

#define MAX_PACKET_LEN 3

#define NO_OF_PACKETS 1

#define MAX_DATA_BUFFER_SIZE NO_OF_PACKETS*MAX_PACKET_LEN

 

Does anyone know why RDFO is always zero?

 

communicaiton_block_diagram.jpg
FIFO_data.jpg
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