11-27-2019 07:04 AM
If I'm correct, PG142 does not mention how to calculate the actual baud-rate error, nor does the custom IP dialog display this. Is there any way we can check the baud-rate error vs AXI input clock? Any formula for this?
01-05-2020 10:26 AM - edited 01-05-2020 01:17 PM
The following post says the UARTlite baud rate error is limited to 3% in the newer versions of Vivado.
It is sometimes fun to guess a little about what's going on under the hood.
From playing with the AXI UARTlite (2.0) wizard, it appears that the IP is using 16x oversampling to create the UART output waveform. So, from the AXI CLK, CLKA, frequency that you specify in the wizard, the IP must generate an oversampling clock, CLKOS, that is 16x the specified Baud Rate. Further, it appears that CLKOS is created by simple integer division of CLKA. So, the baud rate error depends directly on the accuracy of CLKOS.
For example, if CLKA=100MHz and baud=460800 bits-per-second (bps) then [100,000,000/(16*460800))=13.56. So, CLKOS would be created by dividing CLKA by 14 and the resulting error in CLKOS (and in baud) is 3.12%. Indeed, the wizard does not allow us to select baud=460800 when CLKA=100MHz because the resulting baud error is over the allowed 3%.
However, if CLKA=73.728MHz then this divides evenly into almost all the allowed baud rates times 16x. In fact, when CLKA=73.728MHz, the wizard allows us to select baud=921600 bps.