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plasmaphase
Observer
Observer
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Registered: ‎10-23-2018

AXI VIP 'IF' is not declared under prefix 'inst'

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Although I've found a few references to this issue, I don't think I found a formal fix.  I'm running Vivado 2020.1.1, and trying to simulate using AXI VIP.  I've isolated the problem such that changing vlog.prj file from:

# compile verilog/system verilog design source files
sv xil_defaultlib --include "../../../../CountBits.ip_user_files/ipstatic/hdl" --include "/tools/Xilinx/Vivado/2020.1/data/xilinx_vip/include" \
"../../../../CountBits.srcs/sources_1/ip/axi_vip_1/sim/axi_vip_1_pkg.sv" \
"../../../../CountBits.srcs/sources_1/ip/axi_vip_1/sim/axi_vip_1.sv" \
"../../../../CountBits.srcs/sources_1/ip/axi_vip_0/sim/axi_vip_0_pkg.sv" \
"../../../../CountBits.srcs/sources_1/ip/axi_vip_0/sim/axi_vip_0.sv" \
"../../../../CountBits.srcs/sources_1/ip/axil_vip_0/sim/axil_vip_0_pkg.sv" \
"../../../../CountBits.srcs/sources_1/ip/axil_vip_0/sim/axil_vip_0.sv" \
"../../../../../sim/cb_sim.sv" \

# compile glbl module
verilog xil_defaultlib "glbl.v"

# Do not sort compile order
nosort

 

to this:

# compile verilog/system verilog design source files
sv xil_defaultlib --include "../../../../CountBits.ip_user_files/ipstatic/hdl" --include "/tools/Xilinx/Vivado/2020.1/data/xilinx_vip/include" \
"../../../../CountBits.srcs/sources_1/ip/axi_vip_0/hdl/axi_vip_v1_1_vl_rfs.sv" \
"../../../../CountBits.srcs/sources_1/ip/axi_vip_1/sim/axi_vip_1_pkg.sv" \
"../../../../CountBits.srcs/sources_1/ip/axi_vip_1/sim/axi_vip_1.sv" \
"../../../../CountBits.srcs/sources_1/ip/axi_vip_0/sim/axi_vip_0_pkg.sv" \
"../../../../CountBits.srcs/sources_1/ip/axi_vip_0/sim/axi_vip_0.sv" \
"../../../../CountBits.srcs/sources_1/ip/axil_vip_0/sim/axil_vip_0_pkg.sv" \
"../../../../CountBits.srcs/sources_1/ip/axil_vip_0/sim/axil_vip_0.sv" \
"../../../../../sim/cb_sim.sv" \

# compile glbl module
verilog xil_defaultlib "glbl.v"

# Do not sort compile order
nosort

 

This is a hack, and doesn't remain when I "reset_project" or when I reset output products, or clean out the sim directory.  I'm really looking for a way for this to be fixed with only an xci file that fully generates all output files with the proper fix.

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florentw
Moderator
Moderator
133 Views
Registered: ‎11-09-2015

Hi @plasmaphase 

You shouldn't have to do this hack. Something might be wrong in the vip name.

Refer to the following article I wrote:

https://forums.xilinx.com/t5/Design-and-Debug-Techniques-Blog/AXI-Basics-3-Master-AXI4-Lite-simulation-with-the-AXI-VIP/ba-p/1058302 


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**

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florentw
Moderator
Moderator
134 Views
Registered: ‎11-09-2015

Hi @plasmaphase 

You shouldn't have to do this hack. Something might be wrong in the vip name.

Refer to the following article I wrote:

https://forums.xilinx.com/t5/Design-and-Debug-Techniques-Blog/AXI-Basics-3-Master-AXI4-Lite-simulation-with-the-AXI-VIP/ba-p/1058302 


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**

View solution in original post

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