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Observer
Observer
1,003 Views
Registered: ‎10-31-2019

AXI Verification IP Simulation

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Hi 

I have written the testbench code to read write form VIP to the Block RAM. But the code not working well.

Pls help me to solve the issue.

Am using Vivado 2018.1 and another issue presented under the two imported pkg as read lines.

The testbench:

import axi_vip_pkg::*;
import design_1_axi_vip_0_0_pkg::*;


module tb();

bit aclk_0=0;
bit aresetn_0=0;

xil_axi_uint                          mtestID;
xil_axi_ulong                       mtestADDR;
xil_axi_len_t                       mtestBurstLength;
xil_axi_size_t                    mtestSize;
xil_axi_burst_t                  mtestBurstType ;
xil_axi_lock_t                    mtestLock;
xil_axi_cache_t                 mtestCacheType = 3;
xil_axi_prot_t                    mtestProtectionType;
xil_axi_region_t                mtestRegion;
xil_axi_qos_t                     mtestQOS;
xil_axi_data_beat              dbeat;
xil_axi_user_beat              usrbeat;
xil_axi_data_beat [31:0]    mtestWUSER;
xil_axi_data_beat              mtestAWUSER = 'h0;
xil_axi_data_beat              mtestARUSER = 0;
xil_axi_data_beat [31:0]    mtestRUSER;
xil_axi_uint                        mtestBUSER = 0;
xil_axi_resp_t                    mtestBresp;
xil_axi_resp_t[31:0]           mtestRresp;

bit [31:0]                           mtestWData = 32'h12345678, mtestWData1 = 32'h87654321, mtestWData2 = 32'h00005678,   mtestWData3 = 32'h1234000;


bit [31:0]                           mtestRData;

always #5ns aclk_0= ~aclk_0;


design_1_wrapper DUT
(
.aclk_0(aclk_0),
.aresetn_0(aresetn_0)

);


// Declare Agent

design_1_axi_vip_0_0_mst_t mst_agent;

initial begin

mst_agent = new("master vip agent", DUT.design_1_i.axi_vip_0.inst.IF);
mst_agent.set_agent_tag("Master VIP");
mst_agent.set_verbosity(400);
mst_agent.start_master();


#50ns
aresetn_0=1;
mtestID = 0;
mtestADDR = 32'hC0000000;
mtestBurstLength = 'd4;

mtestSize= 4'b0100;

mtestBurstType = 2'b01;

mtestLock = 2'b00;
mtestProtectionType = 0;
mtestRegion = 0;
mtestQOS = 0;

#100ns

mst_agent.AXI4_WRITE_BURST(
mtestID,
mtestADDR,
mtestBurstLength,
mtestSize,
mtestBurstType,
mtestLock,
mtestCacheType,
mtestProtectionType,
mtestRegion,
mtestQOS,
mtestAWUSER,
mtestWData,
mtestWUSER,
mtestBresp
);

#1000ns
mst_agent.AXI4_READ_BURST (
mtestID,
mtestADDR,
mtestBurstLength,
mtestSize,
mtestBurstType,
mtestLock,
mtestCacheType,
mtestProtectionType,
mtestRegion,
mtestQOS,
mtestARUSER,
mtestRData,
mtestRresp,
mtestRUSER
);

#2000 $finish;

end
endmodule

 

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Moderator
Moderator
748 Views
Registered: ‎11-09-2015

HI noami9226@ 

Try the example design. It is working fine. It should help you debug your issue


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**

View solution in original post

16 Replies
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Moderator
Moderator
919 Views
Registered: ‎11-09-2015

Hi noami9226@ 

What do you mean by it is not working well? What results do you get?

I have written a similar project in a wiki article a while ago. The Vip is configured as AXI4-Lite but it might still be a good place to start:

https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18842507/Using+the+AXI4+VIP+as+a+master+to+read+and+write+to+an+AXI4-Lite+slave+interface


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Observer
Observer
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Registered: ‎10-31-2019
Yes, the project in a wiki article of AXI4Lite is working well, but when am doing same things for AXI4 full MM as mentioned in my post, the write operation not work. Please try to do AXI4 full MM of the same design in a wiki article and reply me. Thank you in advanced.
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Moderator
Moderator
904 Views
Registered: ‎11-09-2015

Hi noami9226@ 

Again, what do you mean by "the write operation does not work"?

Do you get an error message in the console?


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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Observer
Observer
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Registered: ‎10-31-2019
Sorry sir, the issue in the read operation.
My design is to create the read write operations with burst mode from AXI VIP to BRAM by using AXI4 full MM . I wrote the code mentioned above, when am running the simulation test bench of the design, the write operation is only working and read operation not working. Sir please check the code if it's correct or not.
The second issue, the code is response only for Fixed burst transaction. When am assigning value for the mtestSize, mtestBurstType, mtestLock to create burst transactions the issue presents.
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Observer
Observer
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Registered: ‎10-31-2019
Do you get an error message in the console? Yes sir.
see here, when am assign the values of the size and burst of the transactions:
xil_axi_size_t mtestSize= 3'b010 (8Byte);
xil_axi_burst_t mtestBurstType= 2'b01 (INCR);

the errors appears as shown below:
ERROR: [VRFC 10-2649] an enum variable may only be assigned the same enum typed variable or one of its values [D:/Noami/Final/project_1/project_1.srcs/sim_1/new/tb.sv:17]
ERROR: [VRFC 10-2649] an enum variable may only be assigned the same enum typed variable or one of its values [D:/Noami/Final/project_1/project_1.srcs/sim_1/new/tb.sv:19]
ERROR: [VRFC 10-2787] module tb ignored due to previous errors [D:/Noami/Final/project_1/project_1.srcs/sim_1/new/tb.sv:5]

When am removing that values for the size and burst transactions, the code working as default values:
mtestSize= 3'b000 (1Byte)
mtestBurstType= 2'b00 (Fixed Burst)

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Moderator
Moderator
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Registered: ‎11-09-2015

HI noami9226@ 

What do you have on line 17 and 19 of your test bench file?


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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Observer
Observer
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Registered: ‎10-31-2019
xil_axi_size_t mtestSize= 3'b010;
xil_axi_burst_t mtestBurstType= 2'b01;
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Moderator
Moderator
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Registered: ‎11-09-2015

Hi noami9226@ 

Refer to the example design for the AXI VIP it is doing what you are trying to do. This is how it is set

mtestWDataSize = xil_axi_size_t'(xil_clog2((32)/8));
mtestWBurstType = XIL_AXI_BURST_TYPE_INCR;


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Observer
Observer
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Registered: ‎10-31-2019
mtestWDataSize = xil_axi_size_t'(xil_clog2((32)/8));
mtestWBurstType = XIL_AXI_BURST_TYPE_INCR;

I did same this and the same error message I got.
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Moderator
Moderator
749 Views
Registered: ‎11-09-2015

HI noami9226@ 

Try the example design. It is working fine. It should help you debug your issue


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**

View solution in original post

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Observer
Observer
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Registered: ‎10-31-2019
Okay sir. Thanks
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Contributor
Contributor
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Registered: ‎04-02-2019

I am having the same problem with the axi_vip_pkg not being found in my system verilog test bench (see attachment).

I opened the example design and encountered the same problem.   When the import of axi_vip_pkg not found, the enumerated types of the axi4_write_burst function are unknown (also attachment).   What is the link between the axi_vip_pkg and its physical location?

Annotation 2020-07-14 144038.png
Annotation 2020-07-14 144038-2.png
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Moderator
Moderator
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Registered: ‎11-09-2015

HI @rutabagazuma 

You can ignore this warnings. The code should still simulate. The tool has just some trouble to link these files


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Contributor
Contributor
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Registered: ‎04-02-2019

while it is true that the import failures are warnings the undefined elements are errors and prevent compilation.   I believe the errors are due to the failure of the imports at the top of the file.   Is there a search path associated with the imports that is hidden in vivado?   How does vivado map the import to a physical directory?

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Participant
Participant
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Registered: ‎11-10-2018

Hi @florentw 

I have similar issue with VIP core files not being found. 

florentw, why do you ignor this poster's question???

Is Vivado broken? If so please fess up so we don't continue wasting our time. 

 

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Moderator
Moderator
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Registered: ‎11-09-2015

Hi eskull@0 

This is just due to how the AXI VIP was done. Again the simulation should be working fine if your design is correct.

Only the fact that the library files are shown are not found can be ignored. This should not prevent the compilation. If you have error during compilation, it might be another issue.

If the core itself is not found then you probably have an issue in your test bench code.


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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